84,747 research outputs found

    Development and design of three monitoring instruments for spacecraft charging

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    A set of instruments which provide early detection of potentially dangerous geomagnetic substorm conditions and monitor the spacecraft response are discussed. The set consists of a sensor that measures the characteristic energy of collected electrons or ions from + 100 to - 20,000 V, a logarithmic current density sensor that measures local electron flux and a transient events counter that counts the spurious pulses from electrostatic discharges that couple into the spacecraft wiring harness. Design details and performance characteristics of the three instruments are given. Size, weight, and power requirements are minimized

    Orbit transfer rocket engine integrated control and health monitoring system technology readiness assessment

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    The objectives of this task were to: (1) estimate the technology readiness of an integrated control and health monitoring (ICHM) system for the Aerojet 7500 lbF Orbit Transfer Vehicle engine preliminary design assuming space based operations; and (2) estimate the remaining cost to advance this technology to a NASA defined 'readiness level 6' by 1996 wherein the technology has been demonstrated with a system validation model in a simulated environment. The work was accomplished through the conduct of four subtasks. In subtask 1 the minimally required functions for the control and monitoring system was specified. The elements required to perform these functions were specified in Subtask 2. In Subtask 3, the technology readiness level of each element was assessed. Finally, in Subtask 4, the development cost and schedule requirements were estimated for bringing each element to 'readiness level 6'

    Airborne Advanced Reconfigurable Computer System (ARCS)

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    A digital computer subsystem fault-tolerant concept was defined, and the potential benefits and costs of such a subsystem were assessed when used as the central element of a new transport's flight control system. The derived advanced reconfigurable computer system (ARCS) is a triple-redundant computer subsystem that automatically reconfigures, under multiple fault conditions, from triplex to duplex to simplex operation, with redundancy recovery if the fault condition is transient. The study included criteria development covering factors at the aircraft's operation level that would influence the design of a fault-tolerant system for commercial airline use. A new reliability analysis tool was developed for evaluating redundant, fault-tolerant system availability and survivability; and a stringent digital system software design methodology was used to achieve design/implementation visibility

    Design methods for fault-tolerant navigation computers

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    Design methods for fault tolerant navigation computer

    A watchdog processor to detect data and control flow errors

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    A watchdog processor for the MOTOROLA M68040 microprocessor is presented. Its main task is to protect from transient faults caused by SEUs the transmission of data between the processor and the system memory, and to ensure a correct instructions' flow, just monitoring the external bus, without modifying the internal architecture of the M68040. A description of the principal procedures is given, together with the method used for monitoring the instructions' flow

    Automotive Stirling Engine Development Program

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    Mod I engine testing and test results, the test of a Mod I engine in the United States, Mod I engine characterization and analysis, Mod I Transient Test Bed fuel economy, Mod I-A engine performance are discussed. Stirling engine reference engine manufacturing and reduced size studies, components and subsystems, and the study and test of low-cost casting alloys are also covered. The overall program philosophy is outlined, and data and results are presented

    Online and Offline BIST in IP-Core Design

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    This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

    Experimental analysis of computer system dependability

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    This paper reviews an area which has evolved over the past 15 years: experimental analysis of computer system dependability. Methodologies and advances are discussed for three basic approaches used in the area: simulated fault injection, physical fault injection, and measurement-based analysis. The three approaches are suited, respectively, to dependability evaluation in the three phases of a system's life: design phase, prototype phase, and operational phase. Before the discussion of these phases, several statistical techniques used in the area are introduced. For each phase, a classification of research methods or study topics is outlined, followed by discussion of these methods or topics as well as representative studies. The statistical techniques introduced include the estimation of parameters and confidence intervals, probability distribution characterization, and several multivariate analysis methods. Importance sampling, a statistical technique used to accelerate Monte Carlo simulation, is also introduced. The discussion of simulated fault injection covers electrical-level, logic-level, and function-level fault injection methods as well as representative simulation environments such as FOCUS and DEPEND. The discussion of physical fault injection covers hardware, software, and radiation fault injection methods as well as several software and hybrid tools including FIAT, FERARI, HYBRID, and FINE. The discussion of measurement-based analysis covers measurement and data processing techniques, basic error characterization, dependency analysis, Markov reward modeling, software-dependability, and fault diagnosis. The discussion involves several important issues studies in the area, including fault models, fast simulation techniques, workload/failure dependency, correlated failures, and software fault tolerance
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