Optimizing hardware function evaluation

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Customisable arithmetic hardware designs

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Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers

Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this quantum assembly to electric signals (called control pulses) that implement the specified computation on specific physical devices. However, there is a mismatch between the operations defined by the 1- and 2-qubit logical ISA and their underlying physical implementation, so the current practice of directly translating logical instructions into control pulses results in inefficient, high-latency programs. To address this inefficiency, we propose a universal quantum compilation methodology that aggregates multiple logical operations into larger units that manipulate up to 10 qubits at a time. Our methodology then optimizes these aggregates by (1) finding commutative intermediate operations that result in more efficient schedules and (2) creating custom control pulses optimized for the aggregate (instead of individual 1- and 2-qubit operations). Compared to the standard gate-based compilation, the proposed approach realizes a deeper vertical integration of high-level quantum software and low-level, physical quantum hardware. We evaluate our approach on important near-term quantum applications on simulations of superconducting quantum architectures. Our proposed approach provides a mean speedup of $5\times$, with a maximum of $10\times$. Because latency directly affects the feasibility of quantum computation, our results not only improve performance but also have the potential to enable quantum computation sooner than otherwise possible.Comment: 13 pages, to apper in ASPLO

AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture

CPU-FPGA heterogeneous architectures are attracting ever-increasing attention in an attempt to advance computational capabilities and energy efficiency in today's datacenters. These architectures provide programmers with the ability to reprogram the FPGAs for flexible acceleration of many workloads. Nonetheless, this advantage is often overshadowed by the poor programmability of FPGAs whose programming is conventionally a RTL design practice. Although recent advances in high-level synthesis (HLS) significantly improve the FPGA programmability, it still leaves programmers facing the challenge of identifying the optimal design configuration in a tremendous design space. This paper aims to address this challenge and pave the path from software programs towards high-quality FPGA accelerators. Specifically, we first propose the composable, parallel and pipeline (CPP) microarchitecture as a template of accelerator designs. Such a well-defined template is able to support efficient accelerator designs for a broad class of computation kernels, and more importantly, drastically reduce the design space. Also, we introduce an analytical model to capture the performance and resource trade-offs among different design configurations of the CPP microarchitecture, which lays the foundation for fast design space exploration. On top of the CPP microarchitecture and its analytical model, we develop the AutoAccel framework to make the entire accelerator generation automated. AutoAccel accepts a software program as an input and performs a series of code transformations based on the result of the analytical-model-based design space exploration to construct the desired CPP microarchitecture. Our experiments show that the AutoAccel-generated accelerators outperform their corresponding software implementations by an average of 72x for a broad class of computation kernels

Assessment of digital image correlation measurement errors: methodology and results

Optical full-field measurement methods such as Digital Image Correlation (DIC) are increasingly used in the field of experimental mechanics, but they still suffer from a lack of information about their metrological performances. To assess the performance of DIC techniques and give some practical rules for users, a collaborative work has been carried out by the Workgroup “Metrology” of the French CNRS research network 2519 “MCIMS (Mesures de Champs et Identification en Mécanique des Solides / Full-field measurement and identification in solid mechanics, http://www.ifma.fr/lami/gdr2519)”. A methodology is proposed to assess the metrological performances of the image processing algorithms that constitute their main component, the knowledge of which being required for a global assessment of the whole measurement system. The study is based on displacement error assessment from synthetic speckle images. Series of synthetic reference and deformed images with random patterns have been generated, assuming a sinusoidal displacement field with various frequencies and amplitudes. Displacements are evaluated by several DIC packages based on various formulations and used in the French community. Evaluated displacements are compared with the exact imposed values and errors are statistically analyzed. Results show general trends rather independent of the implementations but strongly correlated with the assumptions of the underlying algorithms. Various error regimes are identified, for which the dependence of the uncertainty with the parameters of the algorithms, such as subset size, gray level interpolation or shape functions, is discussed