mm-Wave Silicon ICs: Challenges and Opportunities

Millimeter-waves offer promising opportunities and interesting challenges to silicon integrated circuit and system designers. These challenges go beyond standard circuit design questions and span a broader range of topics including wave propagation, antenna design, and communication channel capacity limits. It is only meaningful to evaluate the benefits and shortcoming of silicon-based mm-wave integrated circuits in this broader context. This paper reviews some of these issues and presents several solutions to them

Gain Enhancement of On-Chip Wireless interconnects at 60 GHz Using an Artificial Magnetic Conductor

The motivation for this work comes from the increased demand for short range high frequency data communication within and between integrated circuit (IC) chips. The use of wireless interconnects introduces flexibility to the circuit design, reduces power consumption and production costs, since the antennas can be integrated into a standard CMOS process. These findings have been well noted in literature. In addition, wireless interconnects operating in the mm-wave frequency range, at 60GHz, allow for a high data rate of over 1Gb/s for short range of transmissions. The drawback of wireless interconnects operating at high frequencies is the distortion in the radiation pattern caused by the silicon substrate inherent in a standard CMOS process. The high permittivity and a low resistivity of silicon in a CMOS process introduce radiation losses. These losses distort the radiating signal, reducing the directive gain and the antenna efficiency. The objective of the work is to enhance antenna gain and improve the radiation efficiency with the use of a Jerusalem-Cross Artificial Magnetic Conductor (AMC). The Jerusalem Cross AMC can mitigate the effects of the silicon and improve data transmission for inter-Chip data communications. A Yagi antenna was optimized for end-fire radiation in the plane of the chip. It’s performance was studied when it was placed in the center and along the front edge of a standard 10mm by 10mm chip, with the AMC layer extending only below the feed system, Partial AMC, and then compared when it extends under the entire antenna, Full AMC. To examine the transmission characteristics two chips were placed facing one another, on an FR4 slab, with the antennas first placed at the front edges of both chips then in the center of their respective chips. For direct comparison a third configuration was made with one antenna in the center of a chip and the other at the edge of the second chip. The performance of this inter-chip transmission was examined with the three AMC layer configurations: No AMC, Partial AMC, and Full AMC. All simulations were performed using ANSYS HFSS. The results show that the partial AMC improves the performance of the Yagi antenna when it was placed at the front edge of the chip facing out. The directive gain (Endfire direction) with the partial AMC was increased by 0.79 dB or 46% when compared to the antenna without an AMC. The radiation efficiency increased from 39% to 45%. When examining the antenna in the center of the larger substrate the full AMC layer improved performance. The directive gain increased by 0.93 dB or 5%. The full AMC layer improved the directional gain of the antenna in the center of the chip because it is more susceptible to the effects of the silicon substrate. Whereas when placed at the edge of the chip the antenna is mainly radiating in free space and not as influenced by the losses due to the silicon. Which is why the partial AMC improves radiation performance for the antenna placed at the edge of the chip. This is more clearly shown by the transmission results. When both antennas were placed at the front edges of their respective chips with full AMC layers the gain increased by 11% and the radiation efficiency increases by 12%; while when both antennas are placed in the center the directive gain increases by 26% and the radiation efficiency increases by only 2%. In the model with one antenna at the front edge of the first chip and the other antenna in the center of the second chip the full AMC improved the directive gain by 12% and 29% respectively. Both results show that the full AMC has a positive effect on the directive gain of the antenna, especially when placed in the center of the substrate

A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

A multi-channel receiver operating between 56 GHz and 70 GHz for coverage of different 60 GHz bands worldwide is implemented with a 90 nm Complementary Metal-Oxide Semiconductor (CMOS) process. The receiver containing an LNA, a frequency down-conversion mixer and a variable gain amplifier incorporating a band-pass filter is designed and implemented. This integrated receiver is tested at four channels of centre frequencies 58.3 GHz, 60.5 GHz, 62.6 GHz and 64.8 GHz, employing a frequency plan of an 8 GHz-intermediate frequency (IF). The achieved conversion gain by coarse gain control is between 4.8 dB–54.9 dB. The millimeter-wave receiver circuit is biased with a 1.2V supply voltage. The measured power consumption is 69 mW

Millimeter-wave interconnects for intra- and inter-chip transmission and beam steering in NoC-based multi-chip systems

The primary objective of this work is to investigate the communication capabilities of short-range millimeter-wave (mm-wave) communication among Network-on-Chip (NoC) based multi-core processors integrated on a substrate board. To address the demand for high-performance multi-chip computing systems, the present work studies the transmission coefficients between the on-chip antennas system for both intra- and inter-chip communication. It addresses techniques for enhancing transmission by using antenna arrays for beamforming. It also explores new and creative solutions to minimize the adverse effects of silicon on electromagnetic wave propagation using artificial magnetic conductors (AMC). The following summarizes the work performed and future work. Intra- and inter-chip transmission between wireless interconnects implemented as antennas on-chip (AoC), in a wire-bonded chip package are studied 30GHz and 60 GHz. The simulations are performed in ANSYS HFSS, which is based on the finite element method (FEM), to study the transmission and to analyze the electric field distribution. Simulation results have been validated with fabricated antennas at 30 GHz arranged in different orientations on silicon dies that can communicate with inter-chip transmission coefficients ranging from -45dB to -60dB while sustaining bandwidths up to 7GHz. The fabricated antennas show a shift in the resonant frequency to 25GHz. This shift is attributed to the Ground-Signal-Ground (GSG) probes used for measurement and to the Short-Open-Load (SOLT) calibration which has anomalies at millimeter-wave frequencies. Using measurements, a large-scale log-normal channel model is derived which can be used for system-level architecture design. Further, at 60 GHz densely packed multilayer copper wires in NoCs have been modeled to study their impact on the wireless transmission between antennas for both intra- and inter-chip links and are shown to be equivalent to copper sheets. It is seen that the antenna radiation efficiency reduces in the presence of these densely packed wires placed close to the antenna elements. Using this model, the reduction of inter-chip transmission is seen to be about 20dB as compared to a system with no wires. Lastly, the transmission characteristics of the antennas resonating at 60GHz in a flip-chip packaging environment are also presented

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

Wireless Interconnects for Intra-chip & Inter-chip Transmission

With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved. This thesis presents study of transmission between zigzag antennas as wireless interconnects for Multichip multicores (MCMC) systems and 3D IC. For MCMC systems, a four-chips 16-cores model is analyzed with only four wireless interconnects in three configurations with different antenna orientations and locations. Return loss and transmission coefficients are simulated in ANSYS HFSS. Moreover, wireless interconnects are designed, fabricated and tested on a 6’’ silicon wafer with resistivity of 55Ω-cm using a basic standard CMOS process. Wireless interconnect are designed to work at 30GHz using ANSYS HFSS. The fabricated antennas are resonating around 20GHz with a return loss of less than -10dB. The transmission coefficients between antenna pair within a 20mm x 20mm silicon die is found to be varying between -45dB to -55dB. Furthermore, wireless interconnect approach is extended for 3D IC. Wireless interconnects are implemented as zigzag antenna. This thesis extends the work of analyzing the wireless interconnects in 3D IC with different configurations of antenna orientations and coolants. The return loss and transmission coefficients are simulated using ANSYS HFSS

mm-Wave Systems for High Data Rate Wireless Consumer Applications

ISM spectrum at 60GHz has attracted attention for possible high-speed applications in wireless communications for well over ten years. However, no high volume applications have emerged. Despite progress in mm-wave ICs, the power and cost of these efforts have not reached the level needed for mass deployment. This paper summarises the ARC funded GLIMMR project which aims to remedy this situation by designing systems on silicon that have both low cost and low power. In particular, the paper presents design work done to date that indicate that silicon (particularly SiGe) is on the cusp of being able to provide economical mm-wave systems