Millimeter-wave Communication and Radar Sensing — Opportunities, Challenges, and Solutions

With the development of communication and radar sensing technology, people are able to seek for a more convenient life and better experiences. The fifth generation (5G) mobile network provides high speed communication and internet services with a data rate up to several gigabit per second (Gbps). In addition, 5G offers great opportunities of emerging applications, for example, manufacture automation with the help of precise wireless sensing. For future communication and sensing systems, increasing capacity and accuracy is desired, which can be realized at millimeter-wave spectrum from 30 GHz to 300 GHz with several tens of GHz available bandwidth. Wavelength reduces at higher frequency, this implies more compact transceivers and antennas, and high sensing accuracy and imaging resolution. Challenges arise with these application opportunities when it comes to realizing prototype or demonstrators in practice. This thesis proposes some of the solutions addressing such challenges in a laboratory environment.High data rate millimeter-wave transmission experiments have been demonstrated with the help of advanced instrumentations. These demonstrations show the potential of transceiver chipsets. On the other hand, the real-time communication demonstrations are limited to either low modulation order signals or low symbol rate transmissions. The reason for that is the lack of commercially available high-speed analog-to-digital converters (ADCs); therefore, conventional digital synchronization methods are difficult to implement in real-time systems at very high data rates. In this thesis, two synchronous baseband receivers are proposed with carrier recovery subsystems which only require low-speed ADCs [A][B].Besides synchronization, high-frequency signal generation is also a challenge in millimeter-wave communications. The frequency divider is a critical component of a millimeter-wave frequency synthesizer. Having both wide locking range and high working frequencies is a challenge. In this thesis, a tunable delay gated ring oscillator topology is proposed for dual-mode operation and bandwidth extension [C]. Millimeter-wave radar offers advantages for high accuracy sensing. Traditional millimeter-wave radar with frequency-modulated continuous-wave (FMCW), or continuous-wave (CW), all have their disadvantages. Typically, the FMCW radar cannot share the spectrum with other FMCW radars.\ua0 With limited bandwidth, the number of FMCW radars that could coexist in the same area is limited. CW radars have a limited ambiguous distance of a wavelength. In this thesis, a phase-modulated radar with micrometer accuracy is presented [D]. It is applicable in a multi-radar scenario without occupying more bandwidth, and its ambiguous distance is also much larger than the CW radar. Orthogonal frequency-division multiplexing (OFDM) radar has similar properties. However, its traditional fast calculation method, fast Fourier transform (FFT), limits its measurement accuracy. In this thesis, an accuracy enhancement technique is introduced to increase the measurement accuracy up to the micrometer level [E]

PHY Link Design and Optimization For High-Speed Low-Power Communication Systems

The ever-growing demands for high-bandwidth data transfer have been pushing towards advancing research efforts in the field of high-performing communication systems. Studies on the performance of single chip, e.g. faster multi-core processors and higher system memory capacity, have been explored. To further enhance the system performance, researches have been focused on the improvement of data-transfer bandwidth for chip-to-chip communication in the high-speed serial link. Many solutions have been addressed to overcome the bottleneck caused by the non-idealties such as bandwidth-limited electrical channel that connects two link devices and varieties of undesired noise in the communication systems. Nevertheless, with these solutions data have run into limitations of the timing margins for high-speed interfaces running at multiple gigabits per second data rates on low-cost Printed Circuit Board (PCB) material with constrained power budget. Therefore, the challenge in designing a physical layer (PHY) link for high-speed communication systems turns out to be power-efficient, reliable and cost-effective. In this context, this dissertation is intended to focus on architectural design, system-level and circuit-level verification of a PHY link as well as system performance optimization in respective of power, reliability and adaptability in high-speed communication systems. The PHY is mainly composed of clock data recovery (CDR), equalizers (EQs) and high- speed I/O drivers. Symmetrical structure of the PHY link is usually duplicated in both link devices for bidirectional data transmission. By introducing training mechanisms into high-speed communication systems, the timing in one link device is adaptively aligned to the timing condition specified in the other link device despite of different skews or induced jitter resulting from process, voltage and temperature (PVT) variations in the individual link. With reliable timing relationships among the interface signals provided, the total system bandwidth is dramatically improved. On the other hand, interface training offers high flexibility for reuse without further investigation on high demanding components involved in high costs. In the training mode, a CDR module is essential for reconstructing the transmitted bitstream to achieve the best data eye and to detect the edges of data stream in asynchronous systems or source-synchronous systems. Generally, the CDR works as a feedback control system that aligns its output clock to the center of the received data. In systems that contain multiple data links, the overall CDR power consumption increases linearly with the increase in number of links as one CDR is required for each link. Therefore, a power-efficient CDR plays a significant role in such systems with parallel links. Furthermore, a high performance CDR requires low jitter generation in spite of high input jitter. To minimize the trade-off between power consumption and CDR jitter, a novel CDR architecture is proposed by utilizing the proportional-integral (PI) controller and three times sampling scheme. Meanwhile, signal integrity (SI) becomes critical as the data rate exceeds several gigabits per second. Distorted data due to the non-idealties in systems are likely to reduce the signal quality aggressively and result in intolerable transmission errors in worst case scenarios, thus affect the system effective bandwidth. Hence, additional trainings such as transmitter (Tx) and receiver (Rx) EQ trainings for SI purpose are inserted into the interface training. Besides, a simplified system architecture with unsymmetrical placement of adaptive Rx and Tx EQs in a single link device is proposed and analyzed by using different coefficient adaptation algorithms. This architecture enables to reduce a large number of EQs through the training, especially in case of parallel links. Meanwhile, considerable power and chip area are saved. Finally, high-speed I/O driver against PVT variations is discussed. Critical issues such as overshoot and undershoot interfering with the data are primarily accompanied by impedance mismatch between the I/O driver and its transmitting channel. By applying PVT compensation technique I/O driver impedances can be effectively calibrated close to the target value. Different digital impedance calibration algorithms against PVT variations are implemented and compared for achieving fast calibration and low power requirements

Power and spectrally efficient integrated high-speed LED drivers for visible light communication

Recent trends in mobile broadband indicates that the available radio frequency (RF) spectrum will not be enough to support the data requirements of the immediate future. Visible light communication, which uses visible spectrum to transmit wirelessly could be a potential solution to the RF ’Spectrum Crunch’. Thus there is growing interest all over the world in this domain with support from both academia and industry. Visible light communication( VLC) systems make use of light emitting diodes (LEDs), which are semiconductor light sources to transmit information. A number of demonstrators at different data capacity and link distances has been reported in this area. One of the key problems holding this technology from taking off is the unavailability of power efficient, miniature LED drive schemes. Reported demonstrators, mostly using either off the shelf components or arbitrary waveform generators (AWGs) to drive the LEDs have only started to address this problem by adopting integrated drivers designed for driving lighting installations for communications. The voltage regulator based drive schemes provide high power efficiency (> 90 %) but it is difficult to realise the fast switching required to achieve the Mbps or Gbps data rates needed for modern wireless communication devices. In this work, we are exploiting CMOS technology to realise an integrated LED driver for VLC. Instead of using conventional drive schemes (digital to analogue converter (DAC) + power amplifier or voltage regulators), we realised a current steering DAC based LED driver operating at high currents and sampling rates whilst maintaining power efficiency. Compared to a commercial AWG or discrete LED driver, circuit realised utilisng complementary metal oxide semiconductor (CMOS) technology has resulted in area reduction (29mm2). We realised for the first time a multi-channel CMOS LED driver capable of operating up to a 500 MHz sample rate at an output current of 255 mA per channel and >70% power efficiency. We were able to demonstrate the flexibility of the driver by employing it to realise VLC links using micro LEDs and commercial LEDs. Data rates up to 1 Gbps were achieved using this system employing a multiple input, multiple output (MIMO) scheme. We also demonstrated the wavelength division multiplexing ability of the driver using a red/green/blue commercial LED. The first integrated digital to light converter (DLC), where depending on the input code, a proportional number of LEDs are turned ON, realising a data converter in the optical domain, is also an output from this research. In addition, we propose a differential optical drive scheme where two output branches of a current DAC are used to drive two LEDs achieving higher link performance and power efficiency compared to single LED drive

Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un

Reducing jitter utilising adaptive pre-emphasis FIR filter for high speed serial links

Jitter requirements have become more stringent with higher speed serial communication links. Reducing jitter, with the main focus on reducing data dependant jitter (DDJ), is presented by employing adaptive finite impulse response (FIR) filter pre-emphasis. The adaptive FIR pre-emphasis is implemented in the IBM 7WL 0.18 µm SiGe BiCMOS process. SiGe heterojunction bipolar transistors (HBTs) provide high bandwidth, low noise devices which could reduce the total system jitter. The trade-offs between utilising metal oxide semiconductor (MOS) current mode logic (CML) and SiGe bipolar CML are also discussed in comparison with a very high fT (IBM 8HP process with fT = 200 GHz) process. A reduction in total system jitter can be achieved by keeping the sub-components of the system jitter constant while optimising the DDJ. High speed CML circuits have been employed to allow data rates in excess of 5 Gb/s to be transmitted whilst still maintaining an internal voltage swing of at least 300 mV. This allows the final FIR filter adaptation scheme to minimise the DDJ within 12.5 % of a unit interval, at a data rate of 5 Gb/s implementing 6 FIR pre-emphasis filter taps, for a worst case copper backplane channel (30" FR-4 channel). The implemented integrated circuit (IC) designed as part of the verification process takes up less than 1 mm2 of silicon real estate. In this dissertation, SPICE simulation results are presented, as well as the novel IC implementation of the proposed FIR filter adaptation technique as part of the hypothesis verification procedure. The implemented transmitter and receiver were tested for functionality, and showed the successful functional behaviour of all the implemented CML gates associated with the first filter tap. However, due to the slow charge and discharge rate of the pulse generation circuit in both the transmitter and receiver, only the main operational state of the transmitter could be experimentally validated. As a result of the adaptation scheme implemented, the contribution in this research lies in that a designer utilising such an IC can optimise the DDJ, reducing the total system jitter, and hence increasing the data fidelity with minimal effort.Dissertation (MEng)--University of Pretoria, 2011.Electrical, Electronic and Computer Engineeringunrestricte

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities