A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM

In this paper, a new memory cell along with a new peripheral circuit for SRAM in ultra fine advanced process technologies is presented. A unique feature of the proposed circuit technique is its circuit design concept to achieve the fully digital ratio-less operation. This enables memory cell design that is free from consideration of the Static Noise Margin (SNM). Furthermore, it enables SRAM function without the restriction of transistor parameter (W/L) settings in circuit design and the dependency on local process variation. To achieve these unique features, we propose (1) a ratio-less memory cell in which the flip/flop loop can be broken in write operation and a push-pull tri-state buffer for secure read operation and (2) the configuration of a static Column Retention Loop (CRL) to prevent loss of memory cell data in the write half-select state. Combining these two key circuit techniques, a new SRAM circuit that is free from design restriction of SNM was developed. A 0.18-μm 1024-bit MOSAIC SRAM TEG consisting of memory cells having all combinations of gate sizes of 10 transistors differing by two orders of magnitude was developed and tested to verify the proposed circuits.4th IEEE International Memory Workshop (IMW 2012), 20-23 May 2012, Milan, Ital

ULTRALOW-POWER, LOW-VOLTAGE DIGITAL CIRCUITS FOR BIOMEDICAL SENSOR NODES

Ph.DDOCTOR OF PHILOSOPH

Energy-Efficient Time-Based Encoders and Digital Signal Processors in Continuous Time

Continuous-time (CT) data conversion and continuous-time digital signal processing (DSP) are an interesting alternative to conventional methods of signal conversion and processing. This alternative proposes time-based encoding that may not suffer from aliasing; shows superior spectral properties (e.g. no quantization noise floor); and enables time-based, event-driven, flexible signal processing using digital circuits, thus scaling well with technology. Despite these interesting features, this approach has so far been limited by the CT encoder, due to both its relatively poor energy efficiency and the constraints it imposes on the subsequent CT DSP. In this thesis, we present three principles that address these limitations and help improve the CT ADC/DSP system. First, an adaptive-resolution encoding scheme that achieves first-order reconstruction with simple circuitry is proposed. It is shown that for certain signals, the scheme can significantly reduce the number of samples generated per unit of time for a given accuracy compared to schemes based on zero-order-hold reconstruction, thus promising to lead to low dynamic power dissipation at the system level. Presented next is a novel time-based CT ADC architecture, and associated encoding scheme, that allows a compact, energy-efficient circuit implementation, and achieves first-order quantization error spectral shaping. The design of a test chip, implemented in a 0.65-V 28-nm FDSOI process, that includes this CT ADC and a 10-tap programmable FIR CT DSP to process its output is described. The system achieves 32 dB – 42 dB SNDR over a 10 MHz – 50 MHz bandwidth, occupies 0.093 mm2, and dissipates 15 µW–163 µW as the input amplitude goes from zero to full scale. Finally, an investigation into the possibility of CT encoding using voltage-controlled oscillators is undertaken, and it leads to a CT ADC/DSP system architecture composed primarily of asynchronous digital delays. The latter makes the system highly digital and technology-scaling-friendly and, hence, is particularly attractive from the point of view of technology migration. The design of a test chip, where this delay-based CT ADC/DSP system architecture is used to implement a 16-tap programmable FIR filter, in a 1.2-V 28-nm FDSOI process, is described. Simulations show that the system will achieve a 33 dB – 40 dB SNDR over a 600 MHz bandwidth, while dissipating 4 mW