Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques

The internet-of-things is a growing market segment which is based on an arrayof portable communication devices with high power efficiency. Advanced semiconductortechnology can easily improve their digital performance, but the samecannot be said for the analog blocks which are vital to their operation. Highperformance analog circuits continue to use conventional design techniques andarchitectures at the expense of power efficiency. Deeply scaled CMOS exaggeratesthis trade-off, opening the door for novel system techniques that take advantage ofthe digital nature of sub-micron transistors. This research focuses on two highlydigital ADCs which can mitigate the short channel effects of limited output swingand low intrinsic gain while also benefiting from process scaling.First, a multi-domain ADC is used to perform quantization on both voltageand time domain signals, relaxing the power-performance trade-off. This hybridapproach can lead to a high resolution, high efficiency data converter in scaledprocess. A prototype ADC was fabricated in 180nm CMOS, showing an SNDRof 73 dB, operating at 20 MHz sampling frequency, with a power consumption of1.28 mW.Next, an automated synthesis process is used to automatically generate a highspeed VCO-based quantizer from verilog code. Stochastic spatial averaging iscombined with a high speed open-loop noise-shaping quantizer to provide enhancedresolution in the presence of device mismatch. Simulation results of a prototypeADC in 180nm CMOS shows an SNDR of 49 dB, operating at 800 MHz samplingfrequency and 50 MHz signal bandwidth.Keywords: data converter, synthesis, verilog, ADC, SAR, TD