Design of a 3 GHz fine resolution LC DCO

In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin

Design of CMOS LC voltage controlled oscillators

This work presents the design and implementation of CMOS LC voltage controlled oscillators. On-chip planar spiral inductors and PMOS inversion mode varactors were utilized to implement the resonator. Two voltage controlled oscillators (VCOs) were realized as a part of this work, one designed to operate at 1.1 GHz while the second at 1.8 GHz. Both VCOs were implemented in a scalable digital CMOS process, with the former in a 1.5 micron CMOS process and the latter in a 0.5 micron technology. A simulation based methodology was adopted to arrive at a simple pi model used to model the metal and substrate related losses responsible for deteriorating the integrated inductor\u27s performance. Geometry based optimization techniques were utilized to arrive at an inductor geometry that ensures reasonable quality factor. In addition to the core VCO structure a host of test structures have been incorporated in order to carry out two-port network measurements in the future. Such measurements should enable one to gain a greater insight into the integrated inductor and varactor\u27s performance

A Voltage Controlled Oscillator for a Phase-Locked Loop Frequency Synthesizer in a Silicon-on-Sapphire Process

Engineers from a government-owned engineering and manufacturing facility were contracted by government-owned research laboratory to design and build an S-band telemetry transmitter using Radio Frequency Integrated Circuit (RFIC) technology packaged in a Low-Temperature Co-fired Ceramic (LTCC) Multi-Chip Module. The integrated circuit technology chosen for the Phase-Locked Loop Frequency Synthesizer portion of the telemetry transmitter was a 0.25 um CMOS process that utilizes a sapphire substrate and is fabricated by Peregrine Semiconductor corporation. This thesis work details the design of the Voltage Controlled Oscillator (VCO) portion of the PLL frequency synthesizer and constitutes an fully integrated VCO core circuit and a high-isolation buffer amplifier. The high-isolation buffer amplifier was designed to provide 16 dB of gain for 2200-3495 MHz as well as 60 dB of isolation for the oscillator core to provide immunity to frequency pulling due to RF load mismatch. Actual measurements of the amplifier gain and isolation showed the gain was approximately 5 dB lower than the simulated gain when all bond-wire and test substrate parasitics were taken into account. The isolation measurements were shown to be 28 dB at the high end of the frequency band but the measurement was more than likely compromised due to the aforementioned bond-wire and test substrate parasitics. The S-band oscillator discussed in this work was designed to operate over a frequency range of 2200 to 2300 MHz with a minimum output power of 0 dBm with a phase-noise of -92 dBc/Hz at a 100 kHz offset from the carrier. The tuning range was measured to be from 2215 MHz to 2330 MHz with a minimum output power of -7 dBm over the measured frequency range. A phase-noise of -90 dBc was measured at a 100 kHz offset from the carrier

A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation

Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop accordingly to meet the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices. Specically this entails meeting stringent noise specications imposed by modern wireless standards, meeting low power consumption budgets to prolong battery lifetimes, operating under reduced supply voltages imposed by modern technology nodes and within the noisy environments of complex system-on-chip (SOC) designs, all in addition to consuming as little silicon area as possible. The ability of the PLL to achieve the above is thus key to its continual progress in enabling wireless technology achieve increasingly powerful products which increasingly benet our daily lives. This thesis furthers the development of PLLs with respect to meeting the challenges imposed upon it by modern wireless technology, in two ways. Firstly, the thesis describes in detail the advantages to be gained through employing a fully dierential PLL. Specically, such PLLs are shown to achieve low noise performance, consume less silicon area than their conventional counterparts whilst consuming similar power, and being better suited to the low supply voltages imposed by continual technology downsizing. Secondly, the thesis proposes a sub-banded VCO architecture which, in addition to satisfying simultaneous requirements for large tuning ranges and low phase noise, achieves signicant reductions in PLL loop bandwidth variation. First and foremost, this improves on the stability of the PLL in addition to improving its dynamic locking behaviour whilst oering further improvements in overall noise performance. Since the proposed sub-banded architecture requires no additional power over a conventional sub-banded architecture, the solution thus remains attractive to the realm of low power design. These two developments combine to form a fully dierential PLL with reduced loop bandwidth variation. As such, the resulting PLL is well suited to meeting the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices, and thus applicable to the continual development of wireless technology in benetting our daily lives

Digitally Controlled Oscillator for mm-Wave Frequencies

In the fifth generation of mobile communication, 5G, frequencies above 30 GHz, so-called millimeter-wave (mm-wave) frequencies are expected to play a prominent role. For the synthesis of these frequencies, the all-digital phase locked loop (ADPLL) has recently gained much attention. A core component of the ADPLL is the digitally controlled oscillator (DCO), an oscillator that tunes the frequency discretely. For good performance, the frequency steps must be made very small, while the total tuning range must be large. This thesis covers several coarse- and fine-tuning techniques for DCOs operating at mm-wave frequencies. Three previously not published fine-tuning schemes are presented: The first one tunes the second harmonic, which will, due to the Groszkowski effect, tune the fundamental tone. The second one is a current-modulation scheme, which utilizes the weak current-dependence of the capacitance of a transistor to tune the frequency. In the third one, a digital-to-analog converter (DAC) is connected to the bulk of the differential pair and tunes the frequency by setting the bulk voltage. The advantages and disadvantages of the presented tuning schemes are discussed and compared with previously reported fine-tuning schemes. Two oscillators were implemented at 86 GHz. Both oscillator use the same oscillator core and hence have the same power consumption and tuning range, 14.1 mW and 13.9%. A phase noise of -89.7 dBc/Hz and -111.4 dBc/Hz at 1 MHz and 10 MHz offset, respectively, were achieved, corresponding to a Figure-of-Merit of -178.5 dBc/Hz. The first oscillator is fine-tuned using a combination of a transformer-based fine-tuning and the current modulation scheme presented here. The achieved frequency resolution is 55 kHz, but can easily be made finer. The second oscillator utilizes the bulk bias technique to achieve its fine tuning. The fine-tuning resolution is here dependent on the resolution of the DAC; a 100μV resolution corresponds to a resolution of 50 kHz.n 2011, the global monthly mobile data usage was 0.5 exabytes, or 500 million gigabytes. In 2016, this number had increased to 7 exabytes, an increase by a factor 14 in just five years, and there are no signs of this trend slowing down. To meet the demands of the ever increasing data usage, engineers have begun to investigate the possibility to use significantly higher frequencies, 30 GHz or higher, for mobile communication than what is used today, which is 3 GHz or below. To be able to transmit and receive data at these high frequency, an oscillator capable of operating at these frequencies are required. An oscillator is an electrical circuit that generates an alternating current (a current that first goes one way, and then the other) at a specific frequency. Below is an example to illustrate to function and importance of the oscillator: Imagine driving a car and listening to the radio. Suddenly, a horrendous song starts playing from the radio, so you instantly tune to another station and find some great, smooth jazz. Satisfied, you lean back and drive on. But what exactly happened when you "tuned to another station"? What you really did was changing the frequency of the oscillator, which can be found in the radio receiver of the car. The radio receiver filters out all frequencies, except for the frequency of the local oscillator. So by setting the frequency of the local oscillator to the frequency of the desired radio channel, only this radio channel will reach the speakers of the car. Thus, the oscillator must be able to vary its frequency to any frequency that a radio station can transmit on. While an old car radio may seem like a simple example, the very same principle is used in mobile communication, even at frequencies above 30 GHz. The oscillator is also used in the same way when transmitting signals, so that the signals are transmitted on the correct frequency. The design of the local oscillator is a hot topic among radio engineers. A poorly designed oscillator will ruin the performance of the whole receiver or transmitter. This thesis covers the design of a special type of oscillators, called digital controlled oscillators or DCO, operating at 30 GHz or higher. The frequency of these oscillators are determined by a digital word (ones and zeros), instead of using an analog voltage, which is traditionally used. Digital control results in greater flexibility and higher noise-resilience, but it also means that the frequency can’t be changed continuously, but rather in discrete steps. This discrete behavior will cause noise in the receiver. To minimize this noise, the frequency steps should be minimized. In this thesis, we have proposed a DCO design, operating at 85.5 GHz, which can be tuned almost 7 % in either direction. To our knowledge, no other DCO operates at such high frequencies. In the proposed oscillators the frequency steps are only 55 kHz apart, which is so small that its effect on the radio receiver can, with a good conscience, be ignored. This is achieved with a novel technique that makes tiny, tiny changes in the current that passes through the oscillator

Phase Noise in CMOS Phase-Locked Loop Circuits

Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are investigated in different types of PLL designs. Hot carrier and negative bias temperature instability effects are analyzed from simulations and experiments. Phase noise of a CMOS phase-locked loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant model with additive noise sources in frequency domain is presented to analyze the phase noise. The modeled phase noise results are compared with the corresponding experimentally measured results on phase-locked loop chips fabricated in 0.5 m n-well CMOS process. With the scaling of CMOS technology and the increase of electrical field, MOS transistors have become very sensitive to hot carrier effect (HCE) and negative bias temperature instability (NBTI). These two reliability issues pose challenges to designers for designing of chips in deep submicron CMOS technologies. A new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm CMOS process to analyze the effects under HCE and NBTI. A 3V 1.2 GHz programmable phase-locked loop frequency synthesizer is designed in 0.5 μm CMOS technology. The frequency synthesizer is implemented using LC voltage-controlled oscillator (VCO) and a low power dual-modulus prescaler. The LC VCO working range is from 900MHz to 1.4GHz. Current mode logic (CML) is used in designing high speed D flip-flop in the dual-modulus prescaler circuits for low power consumption. The power consumption of the PLL chip is under 30mW. Fully differential LC VCO is used to provide high oscillation frequency. A new design of LC VCO using carbon nanotube (CNT) wire inductor has been proposed. The PLL design using CNT-LC VCO shows significant improvement in phase noise due to high-Q LC circuit

Study on wideband voltage controlled oscillator and high efficiency power amplifier ICs for wireless communications

制度:新 ; 報告番号:甲3604号 ; 学位の種類:博士(工学) ; 授与年月日:2012/2/20 ; 早大学位記番号:新595