A Low Power Comparator Design for 6-Bit Flash ADC in 90-Nm CMOS

ABSTRACT: The main focus of this paper is to design a "Low power Flash ADC" for ultra-wide band applications using CMOS 90nm technology. Flash ADC consists of a reference generator, array of comparators, 1-out-of N code generator, Fat tree encoder and output D latches. The demanding issues in the design of a low power flash ADC is the design of low power latched comparator. The proposed comparator in this paper is designed using 90nm technology at 0.8V DC voltage source using H SPICE tool. The Simulation results of a 6-bit flash ADC is shown for a sampling frequency up to 1.2GHz showing an average power dissipation of 7.67mW. KEYWORDS: Flash ADC, Preamplifier based latch Comparator, Low power consumption. I.INTRODUCTION Analog to digital converters plays a prominent role to interact with the real world. Flash ADC is the fastest ADC in comparison with other ADC architectures. Flash ADC is the best choice in high speed low resolution applications. It is highly used in high data rate links, high speed instrumentation, radar, digital oscilloscopes and optical communications. Since flash ADC is operating in parallel conversion method, maximum operating frequency in the range of gigahertz is possible. In this paper we are designing a low power, high speed comparator. Here we are combining two recently published research papers to achieve the low power and high speed in ADC. In [2] a Low power flash ADC with 6 bit resolution uses inverter based comparator which consumes a less power of 300 μW at a sampling rate of 50MS/s. In [3] a high speed flash ADC with 6 bit resolution uses differential clocked comparator architecture. Even though the sampling speed is 1GS/s, the comparator block alone consumes 2mW of power. The present work collaborates the above explained two papers in order to fill the gap by proposing a 6 bit flash ADC for high speed applications (up to 5 GS/s) and slightly higher power compared to the inverter based ADC. The proposed ADC employs a modified version of the comparator block presented in [3] to achieve low power and high speed of operation. II.LITERATURE SURVEY R Komar, et.al, proposed "A 0.5V 300μw 50MS/s 180nm 6-bit flash adc using inverter based comparators". This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 0.3mW. S. Sheikhaei, et.al, proposed "A 0.35 μm cmos comparator circuit for high-speed adc applications". A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the hig

A Research on High-Performance Analog-to-Digital Converters in Wireless Communication Systems

博士(工学)法政大学 (Hosei University

Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology

Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-of-the-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM)

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe