Design, Analysis and Implementation of DLL clock generator

In this paper we present design, analysis and implementation of Delay Locked Loop (DLL) based clock generator circuits. In this work a DLL has been proposed the design uses dynamic phase detector (PD) for phase detection. Voltage controlled delay line (VCDL) of proposed DLL consists of twelve delay elements. Current starved inverters have been used as delay element. In this paper, a proposed duty cycle corrector solves the problem of the sensitivity to half transparent (HT) architecture and the stuck locking error in the DLL simultaneously proposed DLL is designed to work at an input frequency of 250MHz. The design also generates an output of 3GHz using a frequency multiplication block. The design uses 180nm CMOS process technology and consumes 1.88mW of power at 1.8V