A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier

A 2.4-GHz, 2.2-W, 2-V fully integrated circular geometry power amplifier with 50 Ω input and output matching is fabricated using 2.5V, 0.35 pm CMOS transistors. It can also produce 450mW using a 1V supply. Harmonic suppression is 64dB or better. An on-chip circular-geometry active-transformer is used to combine several push-pull low-voltage amplifiers efficiently to produce a larger output power while maintaining a 50 Ω match. This new on-chip power combining and impedance matching method uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component such as wirebonds. It also desensitizes the operation of the amplifier to the inductance of bonding wires and makes the design more reproducible. This new topology makes possible a fully-integrated 2.2W, 2.4GHz, low voltage CMOS power amplifier for the first time

Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-Ω match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time

Realization of a single-chip, SiGe:C-based power amplifier for multi-band WiMAX applications

A fully-integrated Multi-Band PA using 0.25 μm SiGe:C process with an output power of above 25 dBm is presented. The behaviour of the amplifier has been optimized for multi-band operation covering, 2.4 GHz, 3.6 GHz and 5.4 GHz (UWB-WiMAX) frequency bands for higher 1-dB compression point and efficiency. Multi-band operation is achieved using multi-stage topology. Parasitic components of active devices are also used as matching components, in turn decreasing the number of matching component. Measurement results of the PA provided the following performance parameters: 1-dB compression point of 20.5 dBm, gain value of 23 dB and efficiency value of %7 operation for the 2.4 GHz band; 1-dB compression point of 25.5 dBm, gain value of 31.5 dB and efficiency value of %17.5 for the 3.6 GHz band; 1-dB compression point of 22.4 dBm, gain value of 24.4 dB and efficiency value of %9.5 for the 5.4 GHz band. Measurement results show that using multi-stage topologies and implementing each parasitic as part of the matching network component has provided a wider-band operation with higher output power levels, above 25 dBm, with SiGe:C process

A fully-integrated 1.8-V, 2.8-W, 1.9-GHz, CMOS power amplifier

This paper demonstrated the first 2-stage, 2.8W, 1.8V, 1.9GHz fully-integrated DAT power amplifier with 50Ω input and output matching using 0.18μm CMOS transistors. It has a small-signal gain of 27dB. The amplifier provides 2.8W of power into a 50Ω load with a PAE of 50%

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-[ohm] input and output matching is demonstrated in 0.18-μm CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm^2

Distributed active transformer - a new power-combining andimpedance-transformation technique

In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistor

The Class-E/F Family of ZVS Switching Amplifiers

A new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced. These class-E/F amplifiers have class-E features such as incorporation of the transistor parasitic capacitance into the circuit, exact truly switching time-domain solutions, and allowance for zero-voltage-switching operation. Additionally, some number of harmonics may be tuned in the fashion of inverse class F in order to achieve more desirable voltage and current waveforms for improved performance. Operational waveforms for several implementations are presented, and efficiency estimates are compared to class-E

High Efficiency, Good phase linearity 0.18 µm CMOS Power Amplifier for MBAN-UWB Applications

This paper presents the design of 3.1-10.6 GHz class AB power amplifier (PA) suitable for medical body area network (MBAN) Ultra-Wide Band (UWB) applications in TSMC 0.18 µm technology. An optimization technique to simultaneously maximize power added efficiency(PAE) and minimize group delay variation is employed. Source and Load-pull contours are used to design inter and output stage matching circuits. The post-layout simulation results indicated that the designed PA has a maximum PAE of 32 % and an output 1-dB compression of 11 dBm at 4 GHz. In addition, a small group delay variation of ± 50 ps was realized over the whole required frequency band . Moreover, the proposed PA has small signal power gain (S21) of 12.5 dB with ripple less than 1.5 dB over the frequency range between 3.1 GHz to 10.6 GHz, while consuming 36 mW

Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

A fully integrated low-power SiGe power amplifier for biomedical applications

In this work, a full-integrated very-low power SiGe Power Amplifier (PA) is realized using the IHP (Innovations for High Performance), 0.25μm-SiGe process. The behaviour of the amplifiers has been optimized for the 2.1-2.4 GHz frequency band for a higher 1-dB compression point and high efficiency at a lower supply voltage. The PA delivers an output power of 3.75 mW and 1.25 mW for 2V and 1V, respectively. The PA measurements yielded the following parameters; gain of 13 dB, 1-dB compression point of 5.7 dBm, and Power-Added-Efficiency of 30% for 2V supply voltage. The PA circuit can go down to 1V of supply voltage with a gain of 10 dB, 1-dB compression point of 1 dBm, and Power-Added-Efficiency of 20%. For both supply voltages, the input and the output of the circuit give good reflection performance. With this performance, the PA circuit may be used for low-power biomedical implanted transceiver systems