Low-noise Amplifier for Neural Recording

With a combination of engineering approaches and neurophysiological knowledge of the central nervous system, a new generation of medical devices is being developed to link groups of neurons with microelectronic systems. By doing this, researchers are acquiring fundamental knowledge of the mechanisms of disease and innovating treatments for disabilities in patients who have a failure of communication along neural pathways. A low-noise and low-power analog front-end circuit is one of the primary requirements for neural recording. The main function for the front-end amplifier is to provide gain over the bandwidth of neural signals and to reject undesired frequency components. The chip developed in this thesis is a field-programmable analog front-end amplifier consisting of 16 programmable channels with tunable frequency response. A capacitively coupled two-stage amplifier is used. The first-stage amplifier is a Low-Noise Amplifier (LNA), as it directly interfaces with the neural recording micro-electrodes; the second stage is a high gain and high swing amplifier. A MOS resistor in the feedback path is used to get tunable low-cut-off frequency and reject the dc offset voltage. Our design builds upon previous recording chips designed by two former graduate stu- dents in our lab. In our design, the circuits are optimized for low noise. Our simulations show the recording channel has a gain of 77.9 dB and input-referred noise of 6.95 µV rms(Root-Mean-Square voltage) over 750 Hz to 6.9 kHz. The chip is fabricated in AMS 0.35 µm CMOS technology for a total die area of 3 x 3 mm 2 and Total Power Dissipation (TPD) of 2.9 mW. To verify the functionality and adherence to the design specifications it will be tested on Printed-Circuit-Board

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

Design and Implementation of a Multi-Channel Field-Programmable Analog Front-End For a Neural Recording System

Neural recording systems have attracted an increasing amount of attention in recent years, and researchers have put major efforts into designing and developing devices that can record and monitor neural activity. Understanding the functionality of neurons can be used to develop neuroprosthetics for restoring damages in the nervous system. An analog front-end block is one of the main components in such systems, by which the neuron signals are amplified and processed for further analysis. In this work, our goal is to design and implement a field-programmable 16-channel analog front-end block, where its programmability is used to deal with process variation in the chip. Each channel consists of a two-stage amplifier as well as a band-pass filter with digitally tunable low corner frequency. The 16 recording channels are designed using four different architectures. The first group of recording channels employs one low-noise amplifier (LNA) as the first-stage amplifier and a fully differential amplifier for the second stage along with an NMOS transistor in the feedback loop. In the second group of architectures, we use an LNA as the first stage and a single-ended amplifier for implementing the second stage. Groups three and four have the same design as groups one and two; however the NMOS transistor in the feedback loop is replaced by two PMOS transistors. In our design, the circuits are optimized for low noise and low power consumption. Simulations result in input-referred noise of 6.9 μVrms over 0.1 Hz to 1 GHz. Our experiments show the recording channel has a gain of 77.5 dB. The chip is fabricated in AMS 0.35 μm CMOS technology for a total die area of 3 mm×3 mm and consumes 2.7 mW power from a 3.3 V supply. Moreover, the chip is tested on a PCB board that can be employed for in-vivo recording

Active C4 electrodes for local field potential recording applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.R01 NS072385 - NINDS NIH HHS; 1R01 NS072385 - NINDS NIH HH

A 64-channel inductively-powered neural recording sensor array

This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377μW.Ministerio de Ciencia e Innovación TEC2009-0844

A 4-mode reconfigurable low noise amplifier for implantable neural recording channels

In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by circuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.Office of Naval Research (USA) N00014-14-1-0355Junta de Andalucía TIC 233

Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation

This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters, and adders. The processor, fabricated in a 0.18- μ m CMOS process, only occupies 0.05 mm 2 and consumes 15 nW from a 0.5 V supply voltage at a signal input rate of 1024 S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N00014-19-1-215

Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces

High-density microelectrode arrays (HDMEAs) feature thousands of recording electrodes in a single chip with an area of few square millimeters. The obtained electrode density is comparable and even higher than the typical density of neuronal cells in cortical cultures. Commercially available HDMEA-based acquisition systems are able to record the neural activity from the whole array at the same time with submillisecond resolution. These devices are a very promising tool and are increasingly used in neuroscience to tackle fundamental questions regarding the complex dynamics of neural networks. Even if electrical or optical stimulation is generally an available feature of such systems, they lack the capability of creating a closed-loop between the biological neural activity and the artificial system. Stimuli are usually sent in an open-loop manner, thus violating the inherent working basis of neural circuits that in nature are constantly reacting to the external environment. This forbids to unravel the real mechanisms behind the behavior of neural networks. The primary objective of this PhD work is to overcome such limitation by creating a fullyreconfigurable processing system capable of providing real-time feedback to the ongoing neural activity recorded with HDMEA platforms. The potentiality of modern heterogeneous FPGAs has been exploited to realize the system. In particular, the Xilinx Zynq All Programmable System on Chip (APSoC) has been used. The device features reconfigurable logic, specialized hardwired blocks, and a dual-core ARM-based processor; the synergy of these components allows to achieve high elaboration performances while maintaining a high level of flexibility and adaptivity. The developed system has been embedded in an acquisition and stimulation setup featuring the following platforms: \u2022 3\ub7Brain BioCam X, a state-of-the-art HDMEA-based acquisition platform capable of recording in parallel from 4096 electrodes at 18 kHz per electrode. \u2022 PlexStim\u2122 Electrical Stimulator System, able to generate electrical stimuli with custom waveforms to 16 different output channels. \u2022 Texas Instruments DLP\uae LightCrafter\u2122 Evaluation Module, capable of projecting 608x684 pixels images with a refresh rate of 60 Hz; it holds the function of optical stimulation. All the features of the system, such as band-pass filtering and spike detection of all the recorded channels, have been validated by means of ex vivo experiments. Very low-latency has been achieved while processing the whole input data stream in real-time. In the case of electrical stimulation the total latency is below 2 ms; when optical stimuli are needed, instead, the total latency is a little higher, being 21 ms in the worst case. The final setup is ready to be used to infer cellular properties by means of closed-loop experiments. As a proof of this concept, it has been successfully used for the clustering and classification of retinal ganglion cells (RGCs) in mice retina. For this experiment, the light-evoked spikes from thousands of RGCs have been correctly recorded and analyzed in real-time. Around 90% of the total clusters have been classified as ON- or OFF-type cells. In addition to the closed-loop system, a denoising prototype has been developed. The main idea is to exploit oversampling techniques to reduce the thermal noise recorded by HDMEAbased acquisition systems. The prototype is capable of processing in real-time all the input signals from the BioCam X, and it is currently being tested to evaluate the performance in terms of signal-to-noise-ratio improvement