2 research outputs found
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Active Noise Shaping Analog-to-Digital Data Converters
Successive-approximation-register (SAR) analog-to-digital converters are popular for medium accuracy, medium speed and low power applications, such as in biomedical applications. They have low latency and simple architecture compared with ΔΣ ADCs. This is because of SAR ADCs’ binary searching scheme. Furthermore, SAR ADCs can apply oversampling and noise shaping schemes which are used in ΔΣ ADCs. As a result, the noise-shaping SAR ADC architecture has received more and more attention as a high resolution and power efficient solution for many sensor applications. In this dissertation, novel configurations have been explored for noise-shaping SAR ADCs for power-efficient and high-accuracy data conversion.
Frist, a first-order noise-shaping (NS) SAR ADC using a two-capacitor based DAC (2-C DAC) is described and discussed. There are only two equal valued capacitors used in the DAC, so the total number of capacitors is much less than in conventional binary weighted DAC. Therefore, the 2-C DAC is good for capacitor matching. Furthermore, this 2-C DAC architecture only samples the reference once, so that the proposed NS SAR ADC doesn’t need a reference buffer on or off chip. An active integrator is implemented and used to contribute an ideal first order noise shaping effect and can be extended to second order noise shaping by adding a few extra capacitors with only one integrator. The ADC was fabricated in 180nm CMOS technology. The prototype occupies 0.25mm2. For a 2kHz signal bandwidth, it achieved 78.9dB SNDR and 87.6dB SFDR with a 32 oversampling ratio (OSR). It consumes 74.2 uW power from 1.5V power supply.
Next, a noise shaping SAR ADC with on-chip digital DAC calibration was proposed and implemented. Correlated double sampling (CDS) and correlated level shifting (CLS) are combined to implement the proposed architecture. With these two techniques, the design specifications for the op-amp used in integrator are relaxed. CDS minimized the effect of DC offset and flicker noise from the op-amp, and CLS boosted the effective DC gain of the op-amp. Therefore, the total power consumption of the op-amp can be decreased by about 50% compared with the same NS SAR ADC performance. Also, an incremental ADC (IADC) based on-chip DAC calibration scheme was proposed and implemented. The proposed calibration scheme will share all blocks in the proposed NS SAR ADC, so it will not increase the complexity of the circuitry. The calibration, it gives a more than 13dB improvement on the SNDR. The proposed ADC was fabricated in 130nm CMOS technology. It achieved 85.1 dB DR, 82.6dB SNDR and 90.9dB SFDR with 32 OSR. It consumes 40uW power from 1.6V power supply which gives a 163dB Schreier Figure of Merit
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A 90.5dB DR 1MHz BW Hybrid Two Step ADC with CT Incremental and SAR ADCs
The sensors in real time data processing IoT devices require high resolution and sub-MHz data converters, usually implemented as Incremental ADCs due to the advantages of oversampling technique and low latency. In discrete time incremental (IDT) ADCs, the sampling switch non-linearity, charge injection degrade the resolution, and power hungry OPAMPs are demanded to provide fast and accurate settling for the switch-capacitor circuits. While the continuous time incremental (ICT) ADCs overcome these issues by removing the sampling switches and it also relax the OPAMPs settling accuracy to save power. A hybrid architecture of ICT ADC and SAR two step ADC is proposed to achieve high resolution at low oversampling ratio (OSR). The first ICT ADCs enable higher resolution, faster conversion speed with lower power consumption. The residual error of the ICT ADC is extracted at the last integrator output and transfers to the 2nd SAR for further conversion. In this architecture, only the mismatch between the cascade of integrators (CoIs) and decimation filter transfer functions causes 1st stage quantization noise leakage which can be solved by increasing opamp parameters instead of increasing the digital decimation filter complexity. In addition, the overall SQNR is independent of the first ICT ADC’s NTF, which gives more freedom to trade-off between the loop stability and DAC errors. A 4bits DRZ DAC with data weighted averaging (DWA) technique is adopted to reduce the clock jitter of DAC, mitigate ISI error and static mismatch errors. Based on this architecture, a 16b resolution, 1MHz signal bandwidth hybrid two step ADC is designed and measurement results are demonstrated. Important sub circuits are introduced and analyzed in detail to get the target resolution. The ADC is fabricated in AKM 180nm CMOS process with 1.8V supply voltage, it achieves a DR of 90.5dB, and SNR/SFDR/SNDR of 82.5dB/85dB/80.5dB over 1MHz BW sampled at 64MHz