11 research outputs found

    Reconfigurable Gate Driver Toward High-Power Efficiency and High-Power Density Converters

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    Les systĂšmes de gestion de l'Ă©nergie exigent des convertisseurs de puissance pour fournir une conversion de puissance adaptĂ©e Ă  diverses utilisations. Il existe diffĂ©rents types de convertisseurs de puissance, tel que les amplificateurs de puissance de classe D, les demi-ponts, les ponts complets, les amplificateurs de puissance de classe E, les convertisseurs buck et derniĂšrement les convertisseurs boost. Prenons par exemple les dispositifs implantables, lorsque l'Ă©nergie est prĂ©levĂ©e de la source principale, des convertisseurs de puissance buck ou boost sont nĂ©cessaires pour traiter l'Ă©nergie de l'entrĂ©e et fournir une Ă©nergie propre et adaptĂ©e aux diffĂ©rentes parties du systĂšme. D'autre part, dans les stations de charge des voitures Ă©lectriques, les nouveaux tĂ©lĂ©phones portables, les stimulateurs neuronaux, etc., l'Ă©nergie sans fil a Ă©tĂ© utilisĂ©e pour assurer une alimentation Ă  distance, et des amplificateurs de puissance de classe E sont dĂ©veloppĂ©s pour accomplir cette tĂąche. Les amplificateurs de puissance de classe D sont un excellent choix pour les casques d'Ă©coute ou les haut-parleurs en raison de leur grande efficacitĂ©. Dans le cas des interfaces de capteurs, les demi-ponts et les ponts complets sont les interfaces appropriĂ©es entre les systĂšmes Ă  faible et Ă  forte puissance. Dans les applications automobiles, l'interface du capteur reçoit le signal du cĂŽtĂ© puissance rĂ©duite et le transmet Ă  un rĂ©seau du cĂŽtĂ© puissance Ă©levĂ©e. En outre, l'interface du capteur doit recevoir un signal du cĂŽtĂ© haute puissance et le convertir vers la cĂŽtĂ© basse puissance. Tous les systĂšmes mentionnĂ©s ci-dessus nĂ©cessitent l'inclusion d'un pilote de porte spĂ©cifique dans les circuits, selon les applications. Les commandes de porte comprennent gĂ©nĂ©ralement un dĂ©calage du niveau de commande niveau supĂ©rieur, le levier de changement de niveau infĂ©rieur, une chaĂźne de tampon, un circuit de verrouillage sous tension, un circuit de temps mort, des portes logiques, un inverseur de Schmitt et un mĂ©canisme de dĂ©marrage. Ces circuits sont nĂ©cessaires pour assurer le bon fonctionnement des systĂšmes de conversion de puissance. Un circuit d'attaque de porte reconfigurable prendrait en charge une vaste gamme de convertisseurs de puissance ayant une tension d'entrĂ©e V[indice IN] et un courant de sortie I[indice Load] variables. L'objectif de ce projet est d'Ă©tudier intensivement les causes de diffĂ©rentes pertes dans les convertisseurs de puissance et de proposer ensuite de nouveaux circuits et mĂ©thodologies dans les diffĂ©rents circuits des conducteurs de porte pour atteindre une conversion de puissance avec une haute efficacitĂ© et densitĂ© de puissance. Nous proposons dans cette thĂšse de nouveaux circuits de gestion des temps mort, un Shapeshifter de niveau plus Ă©levĂ© et un Shapeshifter de niveau infĂ©rieur avec de nouvelles topologies qui ont Ă©tĂ© pleinement caractĂ©risĂ©es expĂ©rimentalement. De plus, l'Ă©quation mathĂ©matique du temps mort optimal pour les faces haute et basse d'un convertisseur buck est dĂ©rivĂ©e et expĂ©rimentalement prouvĂ©e. Les circuits intĂ©grĂ©s personnalisĂ©s et les mĂ©thodologies proposĂ©es sont validĂ©s avec diffĂ©rents convertisseurs de puissance, tels que les convertisseurs semi-pont et en boucle ouverte, en utilisant des composants standard pour dĂ©montrer leur supĂ©rioritĂ© sur les solutions traditionnelles. Les principales contributions de cette recherche ont Ă©tĂ© prĂ©sentĂ©es Ă  sept confĂ©rences prestigieuses, trois articles Ă©valuĂ©s par des pairs, qui ont Ă©tĂ© publiĂ©s ou prĂ©sentĂ©s, et une divulgation d'invention. Une contribution importante de ce travail recherche est la proposition d'un nouveau gĂ©nĂ©rateur actif CMOS intĂ©grĂ© dĂ©diĂ© de signaux sans chevauchement. Ce gĂ©nĂ©rateur a Ă©tĂ© fabriquĂ© Ă  l'aide de la technologie AMS de 0.35”m et consomme 16.8mW Ă  partir d'une tension d'alimentation de 3.3V pour commander de maniĂšre appropriĂ©e les cĂŽtĂ©s bas et haut d'un demi-pont afin d'Ă©liminer la propagation. La puce fabriquĂ©e est validĂ©e de façon expĂ©rimentale avec un demi-pont, qui a Ă©tĂ© mis en Ɠuvre avec des composants disponibles sur le marchĂ© et qui contrĂŽle une charge R-L. Les rĂ©sultats des mesures montrent une rĂ©duction de 40% de la perte totale d'un demi-pont de 45V d'entrĂ©e Ă  1MHz par rapport au fonctionnement du demi-pont sans notre circuit intĂ©grĂ© dĂ©diĂ©. Le circuit principal du circuit d'attaque de grille cĂŽtĂ© haut est le dĂ©caleur de niveau, qui fournit un signal de grande amplitude pour le commutateur de puissance cĂŽtĂ© haut. Une nouvelle structure de dĂ©calage de niveau avec un dĂ©lai de propagation minimal doit ĂȘtre prĂ©sentĂ©e. Nous proposons une nouvelle topologie de dĂ©calage de niveau pour le cĂŽtĂ© haut des drivers de porte afin de produire des convertisseurs de puissance efficaces. Le SL prĂ©sente des dĂ©lais de propagation mesurĂ©s de 7.6ns. Les rĂ©sultats mesurĂ©s montrent le fonctionnement du circuit prĂ©sentĂ© sur la plage de frĂ©quence de 1MHz Ă  130MHz. Le circuit fabriquĂ© consomme 31.5pW de puissance statique et 3.4pJ d'Ă©nergie par transition Ă  1kHz, V[indice DDL] = 0.8V , V[indice DDH] = 3.0V, et une charge capacitive C[indice L] = 0.1pF. La consommation Ă©nergĂ©tique totale mesurĂ©e par rapport Ă  la charge capacitive de 0.1 Ă  100nF est indiquĂ©e. Un autre nouveau dĂ©calage vers le bas est proposĂ© pour ĂȘtre utilisĂ© sur le cĂŽtĂ© bas des pilotes de portes. Ce circuit est Ă©galement nĂ©cessaire dans la partie Rₓ du rĂ©seau de bus de donnĂ©es pour recevoir le signal haute tension du rĂ©seau et dĂ©livrer un signal de faible amplitude Ă  la partie basse tension. L'une des principales contributions de ces travaux est la proposition d'un modĂšle de rĂ©fĂ©rence pour l'abaissement de niveau Ă  puissance unique reconfigurable. Le circuit proposĂ© pilote avec succĂšs une gamme de charges capacitives allant de 10fF Ă  350pF. Le circuit prĂ©sentĂ© consomme des puissances statiques et dynamiques de 62.37pW et 108.9”W, respectivement, Ă  partir d'une alimentation de 3.3V lorsqu'il fonctionne Ă  1MHz et pilote une charge capacitive de 10pF. Les rĂ©sultats de la simulation post-layout montrent que les dĂ©lais de propagation de chute et de montĂ©e dans les trois configurations sont respectivement de l'ordre de 0.54 Ă  26.5ns et de 11.2 Ă  117.2ns. La puce occupe une surface de 80”m × 100”m. En effet, les temps morts des cĂŽtĂ©s hauts et bas varient en raison de la diffĂ©rence de fonctionnement des commutateurs de puissance cĂŽtĂ© haut et cĂŽtĂ© bas, qui sont respectivement en commutation dure et douce. Par consĂ©quent, un gĂ©nĂ©rateur de temps mort reconfigurable asymĂ©trique doit ĂȘtre ajoutĂ© aux pilotes de portes traditionnelles pour obtenir une conversion efficace. Notamment, le temps mort asymĂ©trique optimal pour les cĂŽtĂ©s hauts et bas des convertisseurs de puissance Ă  base de Gan doit ĂȘtre fourni par un circuit de commande de grille reconfigurable pour obtenir une conception efficace. Le temps mort optimal pour les convertisseurs de puissance dĂ©pend de la topologie. Une autre contribution importante de ce travail est la dĂ©rivation d'une Ă©quation prĂ©cise du temps mort optimal pour un convertisseur buck. Le gĂ©nĂ©rateur de temps mort asymĂ©trique reconfigurable fabriquĂ© sur mesure est connectĂ© Ă  un convertisseur buck pour valider le fonctionnement du circuit proposĂ© et l'Ă©quation dĂ©rivĂ©e. De plus le rendement d'un convertisseur buck typique avec T[indice DLH] minimum et T[indice DHL] optimal (basĂ© sur l'Ă©quation dĂ©rivĂ©e) Ă  I[indice Load] = 25mA est amĂ©liorĂ© de 12% par rapport Ă  un convertisseur avec un temps mort fixe de T[indice DLH] = T[indice DHL] = 12ns.Power management systems require power converters to provide appropriate power conversion for various purposes. Class D power amplifiers, half and full bridges, class E power amplifiers, buck converters, and boost converters are different types of power converters. Power efficiency and density are two prominent specifications for designing a power converter. For example, in implantable devices, when power is harvested from the main source, buck or boost power converters are required to receive the power from the input and deliver clean power to different parts of the system. In charge stations of electric cars, new cell phones, neural stimulators, and so on, power is transmitted wirelessly, and Class E power amplifiers are developed to accomplish this task. In headphone or speaker driver applications, Class D power amplifiers are an excellent choice due to their great efficiency. In sensor interfaces, half and full bridges are the appropriate interfaces between the low- and high-power sides of systems. In automotive applications, the sensor interface receives the signal from the low-power side and transmits it to a network on the high-power side. In addition, the sensor interface must receive a signal from the high-power side and convert it down to the low-power side. All the above-summarized systems require a particular gate driver to be included in the circuits depending on the applications. The gate drivers generally consist of the level-up shifter, the level-down shifter, a buffer chain, an under-voltage lock-out circuit, a deadtime circuit, logic gates, the Schmitt trigger, and a bootstrap mechanism. These circuits are necessary to achieve the proper functionality of the power converter systems. A reconfigurable gate driver would support a wide range of power converters with variable input voltage V[subscript IN] and output current I[subscript Load]. The goal of this project is to intensively investigate the causes of different losses in power converters and then propose novel circuits and methodologies in the different circuits of gate drivers to achieve power conversion with high-power efficiency and density. We propose novel deadtime circuits, level-up shifter, and level-down shifter with new topologies that were fully characterized experimentally. Furthermore, the mathematical equation for optimum deadtimes for the high and low sides of a buck converter is derived and proven experimentally. The proposed custom integrated circuits and methodologies are validated with different power converters, such as half bridge and open loop buck converters, using off-the-shelf components to demonstrate their superiority over traditional solutions. The main contributions of this research have been presented in seven high prestigious conferences, three peer-reviewed articles, which have been published or submitted, and one invention disclosure. An important contribution of this research work is the proposal of a novel custom integrated CMOS active non-overlapping signal generator, which was fabricated using the 0.35−”m AMS technology and consumes 16.8mW from a 3.3−V supply voltage to appropriately drive the low and high sides of the half bridge to remove the shoot-through. The fabricated chip is validated experimentally with a half bridge, which was implemented with off-the-shelf components and driving a R-L load. Measurement results show a 40% reduction in the total loss of a 45 − V input 1 − MHz half bridge compared with the half bridge operation without our custom integrated circuit. The main circuit of high-side gate driver is the level-up shifter, which provides a signal with a large amplitude for the high-side power switch. A new level shifter structure with minimal propagation delay must be presented. We propose a novel level shifter topology for the high side of gate drivers to produce efficient power converters. The LS shows measured propagation delays of 7.6ns. The measured results demonstrate the operation of the presented circuit over the frequency range of 1MHz to 130MHz. The fabricated circuit consumes 31.5pW of static power and 3.4pJ of energy per transition at 1kHz, V[subscript DDL] = 0.8V , V[subscript DDH] = 3.0V , and capacitive load C[subscript L] = 0.1pF. The measured total power consumption versus the capacitive load from 0.1pF to 100nF is reported. Another new level-down shifter is proposed to be used on the low side of gate drivers. Another new level-down shifter is proposed to be used on the low side of gate drivers. This circuit is also required in the Rₓ part of the data bus network to receive the high-voltage signal from the network and deliver a signal with a low amplitude to the low-voltage part. An essential contribution of this work is the proposal of a single supply reconfigurable level-down shifter. The proposed circuit successfully drives a range of capacitive load from 10fF to 350pF. The presented circuit consumes static and dynamic powers of 62.37pW and 108.9”W, respectively, from a 3.3 − V supply when working at 1MHz and drives a 10pF capacitive load. The post-layout simulation results show that the fall and rise propagation delays in the three configurations are in the range of 0.54 − 26.5ns and 11.2 − 117.2ns, respectively. Its core occupies an area of 80”m × 100”m. Indeed, the deadtimes for the high and low sides vary due to the difference in the operation of the high- and low-side power switches, which are under hard and soft switching, respectively. Therefore, an asymmetric reconfigurable deadtime generator must be added to the traditional gate drivers to achieve efficient conversion. Notably, the optimal asymmetric deadtime for the high and low sides of GaN-based power converters must be provided by a reconfigurable gate driver to achieve efficient design. The optimum deadtime for power converters depends on the topology. Another important contribution of this work is the derivation of an accurate equation of optimum deadtime for a buck converter. The custom fabricated reconfigurable asymmetric deadtime generator is connected to a buck converter to validate the operation of the proposed circuit and the derived equation. The efficiency of a typical buck converter with minimum T[subscript DLH] and optimal T[subscript DHL] (based on the derived equation) at I[subscript Load] = 25mA is improved by 12% compared to a converter with a fixed deadtime of T[subscript DLH] = T[subscript DHL] = 12ns

    Advances in Piezoelectric Systems: An Application-Based Approach.

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    Topical Workshop on Electronics for Particle Physics

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    The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities

    Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology

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    Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states

    A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain

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    This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125 ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30%by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2A load. The peak efficiency is 81 %

    Topical Workshop on Electronics for Particle Physics

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    High frequency AC power and data distribution system

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    © Cranfield University 2011. All rights reserved. No part of this publication may be reproduced without the written permission of the copyright owner.At present, power delivery issues are becoming a concern with modern state of the art electrical and electronic systems. The existing power networks, namely the centralized power architecture and the DC distributed power systems are struggling to cope with rigorous demands in some application areas. While active research to improve the current system is being relentlessly pursued, a more radical approach proposing a new power distribution system is increasingly drawing attention. High frequency AC (HFAC) power distribution architecture has been identified as a viable alternative to existing and future systems. The HFAC distributed power system (DPS) was initially proposed in the early 80s for space application and since then it has been considered for many modern ground based applications. This dissertation presents a fresh perspective to the problem by challenging the current notion of viewing the HFAC DPS merely as a passive power distribution system. The possibility of converting the existing system to a more intelligent architecture is investigated. Two fundamental features identified to be crucial for this implementation is the ability to communicate and to control power flow between the various power processing structures in the system. Developing the ♯enabling technologiesα is the primary focus of this research. A data modem designed to enable bidirectional multi node communication over the HFAC bus satisfies part of this requirement. The ability to control power flow is achieved by introducing digital control in the front end HFAC inverter. It is shown that intelligent management of the HFAC DPS offer potential efficiency benefits previously not possible in the traditional implementation. At the subsystem level, the front end inverter, the point of load (POL) converter and the communication module are investigated in depth. Extensive mathematical modelling is undertaken to develop optimal design guides to improve performance of the subsystems. Prototypes are constructed and the models are experimentally validated. In the case of the front end inverter, a multi stage inverter with parallel operation capability incorporating digital control is presented. An integral cycle converter is investigated as part of the POL subsystem and optimal synthesis pattern that improves power factor is identified. The communication subsystem constitutes the HFAC data modem described above. The modem emulates Ethernet style communication and interfaces to a host system via a simple serial communication link. All communication over the HFAC bus is performed transparently to the host. This dissertation contributes to the improvements of HFAC DPS at both the system and subsystem levels. At the system level, implementation of intelligent management of the HFAC DPS is shown to be viable and offers opportunities for improved performance and flexibility not previously possible. At the subsystem level, performance improvement to the individual power processing structures in the system is presented.Ph

    Integrated Off-Line Power Converter

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