Low-Power High-Data-Rate Transmitter Design for Biomedical Application

Ph.DDOCTOR OF PHILOSOPH

A 2.4-GHz low power polar transmitter for wireless body area network applications

A 2.4GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the overdriven cascode class-C power amplifier used as the output stage, by dynamically adjusting the bias voltage of the cascode transistor. An equivalent baseband model of the transmitter is presented and used to optimize system parameters and give initial assessment of the achievable performance in terms of efficiency and linearity. Based on these simulations, parameters for transistor-level implementation of the bias circuit are derived. The transmitter is designed in a 65nm CMOS technology. The post layout simulations indicate that the transmitter successfully meets the requirements of the IEEE 802.15.6 standard for wireless body area networks. The simulated amplifier consumes 4.75mA from a 1.2V supply while delivering 1.45dBm of output power with a peak efficiency of 24%. The entire transmitter, including the PLL, consumes 7.5mA

INJECTION-LOCKING TECHNIQUES FOR MULTI-CHANNEL ENERGY EFFICIENT TRANSMITTER

Ph.DDOCTOR OF PHILOSOPH

Ultra Low-Power Frequency Synthesizers for Duty Cycled IoT radios

Internet of Things (IoT), which is one of the main talking points in the electronics industry today, consists of a number of highly miniaturized sensors and actuators which sense the physical environment around us and communicate that information to a central information hub for further processing. This agglomeration of miniaturized sensors helps the system to be deployed in previously impossible arenas such as healthcare (Body Area Networks - BAN), industrial automation, real-time monitoring environmental parameters and so on; thereby greatly improving the quality of life. Since the IoT devices are usually untethered, their energy sources are limited (typically battery powered or energy scavenging) and hence have to consume very low power. Today's IoT systems employ radios that use communication protocols like Bluetooth Smart; which means that they communicate at data rates of a few hundred kb/s to a few Mb/s while consuming around a few mW of power. Even though the power dissipation of these radios have been decreasing steadily over the years, they seem to have reached a lower limit in the recent times. Hence, there is a need to explore other avenues to further reduce this dissipation so as to further improve the energy autonomy of the IoT node. Duty cycling has emerged as a promising alternative in this sense since it involves radios transmitting very short bursts of data at high rates and being asleep the rest of the time. In addition, high data rates proffer the added advantage of reducing network congestion which has become a major problem in IoT owing to the increase in the number of sensor nodes as well as the volume of data they send. But, as the average power (energy) dissipated decreases due to duty cycling, the energy overhead associated with the start-up phase of the radio becomes comparable with the former. Therefore, in order to take full advantage of duty cycling, the radio should be capable of being turned ON/OFF almost instantaneously. Furthermore, the radio of the future should also be able to support easy frequency hopping to improve the system efficiency from an interference point of view. In other words, in addition to high data rate capability, the next generation radios must also be highly agile and have a low energy overhead. All these factors viz. data rate, agility and overhead are mainly dependent on the radio's frequency synthesizer and therefore emphasis needs to be laid on developing new synthesizer architectures which are also amenable to technology scaling. This thesis deals with the evolution of one such all-digital frequency synthesizer; with each step dealing with one of the aforementioned issues. In order to reduce the energy overhead of the synthesizer, FBAR resonators (which are a class of MEMS resonators) are used as the frequency reference instead of a traditional quartz crystal. The FBAR resonators aid the design of fast-startup oscillators as opposed to the long latency associated with the start-up of the crystal oscillator. In addition, the frequency stability of the FBAR lends itself to open-loop architecture which can support very high data rates. Another advantage of the open-loop architecture is the frequency agility which aids easy channel switching for multi-hop architectures, as demonstrated in this thesis

Low-Power High Data-Rate Wireless Transmitter For Medical Implantable Devices

RÉSUMÉ Les émetteurs-récepteurs radiofréquences (RF) sont les circuits de communication les plus communs pour établir des interfaces home-machine dédiées aux dispositifs médicaux implantables. Par exemple, la surveillance continue de paramètres de santé des patients souffrant d'épilepsie nécessite un étage de communication sans-fil capable de garantir un transfert de données rapide, en temps réel, à faible puissance tout en étant implémenté dans un faible volume. La consommation de puissance des dispositifs implantables implique une durée de vie limitée de la batterie qui nécessite alors une chirurgie pour son remplacement, a moins qu’une technique de transfert de puissance sans-fil soit utilisée pour recharger la batterie ou alimenter l’implant a travers les tissus humains. Dans ce projet, nous avons conçu, implémenté et testé un émetteur RF à faible puissance et haut-débit de données opérant à 902-928 MHz de la bande fréquentielle industrielle-scientifique-médicale (ISM) d’Amérique du Nord. Cet émetteur fait partie d'un système de communication bidirectionnel dédié à l’interface sans-fil des dispositifs électroniques implantables et mettables et bénéficie d’une nouvelle approche de modulation par déplacement de fréquence (FSK). Les différentes étapes de conception et d’implémentation de l'architecture proposée pour l'émetteur sont discutées et analysées dans cette thèse. Les blocs de circuits sont réalisés suivant les équations dérivées de la modulation FSK proposée et qui mènera à l'amélioration du débit de données et de la consommation d'énergie. Chaque bloc est implémenté de manière à ce que la consommation d'énergie et la surface de silicium nécessaires soient réduites. L’étage de modulation et le circuit mélangeur ne nécessitent aucun courant continu grâce à leur structure passive.Parmi les circuits originaux, un oscillateur en quadrature contrôlé-en-tension (QVCO) de faible puissance est réalisé pour générer des signaux différentiels en quadrature, rail-à-rail avec deux gammes de fréquences principales de 0.3 à 11.5 MHz et de 3 à 40 MHz. L'étage de sortie énergivore est également amélioré et optimisé pour atteindre une efficacité de puissance de ~ 37%. L'émetteur proposé a été implémenté et fabriqué à la suite de simulations post-layout approfondies.----------ABSTRACT Wireless radio frequency (RF) transceivers are the most common communication front-ends used to realize the human-machine interfaces of medical devices. Continuous monitoring of body behaviour of patients suffering from Epilepsy, for example, requires a wireless communication front-end capable of maintaining a fast, real-time and low-power data communication while implemented in small size. Power budget limitation of the implantable and wearable medical devices obliges engineers to replace or recharge the battery cell through frequent medial surgeries or other power transfer techniques. In this project, a low-power and high data-rate RF transmitter (Tx) operating at North-American Industrial-Scientific-Medical (ISM) frequency band (902-928 MHz) is designed, implemented and tested. This transmitter is a part of a bi-directional transceiver dedicated to the wireless interface of implantable and wearable medical devices and benefits from a new efficient Frequency-Shift Keying (FSK) modulation scheme. Different design and implementation stages of the proposed transmitter architecture are discussed and analyzed in this thesis. The building blocks are realized according to the equations derived from the proposed FSK modulation, which results in improvement in data-rate and power consumption. Each block is implemented such that the power consumption and needed chip area are lowered while the modulation block and the mixer circuit require no DC current due to their passive structure. Among the original blocks, a low-power quadrature voltage-controlled oscillator (QVCO) is achieved to provide differential quadrature rail-to-rail signals with two main frequency ranges of 0.3-11.5 MHz and 3-40 MHz. The power-hungry output stage is also improved and optimized to achieve power efficiency of ~37%. The proposed transmitter was implemented and fabricated following deep characterisation by post-layout simulation. Both simulation and measurement results are discussed and compared with state-of-the-art transmitters showing the contribution of this work in this very popular research field. The Figure-Of-Merit (FOM) was improved, meaning mainly increasing the data-rate and lowering the power consumption of the circuit. The transmitter is implemented using 130 nm CMOS technology with 1.2 V supply voltage. A data-rate of 8 Mb/s was measured while consuming 1.4 mA and resulting in energy consumption of 0.21 nJ/b. The fabricated transmitter has small active silicon area of less than 0.25 mm2

A 110pJ/b multichannel FSK/GMSK/QPSK/p/4-DQPSK transmitter with phase-interpolated dual-injection DLL-based synthesizer employing hybrid FIR

10.1109/ISSCC.2013.6487810Digest of Technical Papers - IEEE International Solid-State Circuits Conference56450-451DTPC