2 research outputs found
Design of Inverter Based CMOS Amplifiers in Deep Nanoscale Technologies
In this work, it is proposed a fully differential ring amplifier topology with a deadzone
voltage created by a CMOS resistor with a biasing circuit to increase the robustness over PVT
variations.
The study focuses on analyzing the performance of the ring amplifier over process,
temperature, and supply voltage variations, in order to guarantee a viable industrial employment
in a 7 nm FinFET CMOS technology node for being used as residue amplifier in ADCs.
A ring amplifier is a small modular amplifier, derived from a ring oscillator. It is simple
enough that it can quickly be designed using only a few inverters, capacitors, and switches. It can
amplify with rail-to-rail output swing, competently charge large capacitive loads using slew-based
charging, and scale well in performance according to process trends.
In typical process corner, a gain of 72 dB is achieved with a settling time of 150 ps.
Throughout the study, the proposed topology is compared with others presented in literature
showing better results over corners and presenting a faster response. The proposed topology isn’t
yet suitable for industry use, because it presents one corner significantly slower than the rest,
namely process corner FF 125 °C, and process corner FS -40 °C with a small oscillation
throughout the entire amplification period.
Nevertheless, it proved itself to be a promising technique, showing a high gain and a fast
settling without oscillation phase, with room for improvement.Neste trabalho, é proposta uma topologia de ring amplifier com a deadzone a ser criada
através de uma resistência CMOS com um circuito de polarização para aumentar a robustez para
as variações PVT.
O estudo foca-se em analisar a performance do ring amplifier nas variações de processo,
temperatura e tensão de alimentação, de forma a garantir um uso viável em indústria na tecnologia
de 7 nm FinFET CMOS, para ser usado como amplificador de resíduo em ADCs.
Um ring amplifier é um pequeno amplificador modular, derivado do ring oscillator. É
simples o suficiente para ser facilmente projetado usando apenas poucos inversores,
condensadores e interruptores. Consegue amplificar com rail-to-rail output swing, carregar
grandes cargas capacitivas com carregamento slew-based e escalar bem em termos de
performance de acordo com o processo.
No typical process corner, foi obtido um ganho de 72 dB com um tempo de estabilização
de 150 ps. Durante o estudo, a topologia proposta é comparada com outras presentes na literatura
mostrando melhores resultados over corners e apresentando uma resposta mais rápida. A
topologia proposta ainda não está preparada para uso industrial uma vez que apresenta um corner
significativamente mais lento que os restantes, nomeadamente, process corner FF 125 °C, e outro
process corner, FS -40 °C, com uma pequena oscilação durante todo o período de amplificação.
Todavia, provou ser uma técnica promissora, apresentando um ganho elevado e uma rápida
estabilização sem fase de oscilação, com espaço para melhoria
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Digital Friendly Continuous-Time Delta-Sigma Analog-to-Digital Converters
Conventional Delta-Sigma analog-to-digital converters (ADCs) utilize operational transconductance amplifiers (OTAs) in their loop filter implementation followed by multi-bit voltage domain quantizers. As CMOS integrated circuit technology scales to smaller geometries, the minimum transistor length and the intrinsic gain of the transistors decrease. Moreover, with process scaling the voltage headroom decreases as well. Therefore, designing OTAs in advanced CMOS processes is becoming increasingly difficult. Additionally, multibit quantizers are becoming more difficult to design due to the decreased voltage headroom and the challenges of low offset and noise requirements.
In this thesis, alternative digital solutions are introduced to replace traditional analog blocks. In the proposed solutions, compressed voltage-domain processing is shifted to the time-domain which benefits from process scaling as the transistors scale down in size and become faster.
First, a novel highly linear VCO-based 1-1 multi stage noise shaping (MASH) delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. A prototype was fabricated in a 65nm CMOS process and achieves 79.7 dB SNDR for a 2MHz signal bandwidth. Second, a novel time-domain phase quantization noise extraction for a VCO-based quantizer is introduced. This technique is independent of the OSR and the input signal amplitude of the VCO-based quantizer making it attractive for higher bandwidth applications. Using this technique, a novel 0-1-1 MASH ADC is presented. The first stage is implemented using a 4-bit SAR ADC. The second and the third stages use a VCO-based quantizer (VCOQ). Behavioral simulation results con�rm second-order noise shaping with a 75dB SNDR for an OSR of 20