Two-Phase DC-DC Buck Converter for Power Amplifier Modulation

This thesis presents the theory, design, layout and a proposal for measurement set up of a synchronous DC-DC buck converter. This converter will be used as the supply modulator of power amplifier of mobile phones. The design is done using 45nm CMOS technology. Pmos and nmos switches are synchronously turns on and off for DC voltage conversion. Second order LC type filter is used to filter out the ac component from output. Two phase interleaving is done to reduce the output ripple voltage. Pulse Width Modulation (PWM) method is used for generating the control signal. Several techniques like dead time control mechanism, reduced gate drive voltage for switches are applied for improving the efficiency of the converter. The operating voltage range of the converter is 3.3-4.2V and it can produce 0.5-3V output voltage with 2W of maximum output power. It has maximum load current of 700mA. The switching frequency of the converter can be varied from 10MHz to 100MHz. The ripple voltage is less than 10mV for 50MHz switching frequency. The converter shows good results in terms of power density and simulated efficiency which are 1.65W/mm2 and 88.5%