Time-Domain/Digital Frequency Synchronized Hysteresis Based Fully Integrated Voltage Regulator

abstract: Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required. The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking. The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

High Efficiency Power Supplies for Multi-mode RF Power Amplifiers in Cellular Handset Applications

Cellular handset evolution requires the front end transmitter to support multiple 3G/4G bands for global roaming, and also to be backward compatible with the existing 2G (quad-band GSM/EDGE) network. The cost and size would be prohibitive if one power amplifier (PA) only supports one band or if multiple supplies are required for multiple PAs. Solutions of interest are based on multi-standard multi-band PAs (e.g. 2 multi-mode PAs instead of 8+ mode-specific PAs), and an efficient power supply that supports these multi-mode PAs. The thesis starts with a study of PA supply architectures and DC-DC converters. A series architecture consisting of a boost converter followed by a buck converter has advantages of low-noise buck converter output, together with the ability to deliver full power at low battery voltages to extend the battery life. The buck converter presents a constant power load for the boost converter, which raises stability concerns. Small-signal control-to-output transfer functions are derived for peak or valley current mode controlled boost converter with a downstream regulated converter modeled as constant power load. It is shown how current mode control provides active damping to ensure stability and well-behaved dynamic response. Furthermore, it is shown how load current feedforward presents an effective way to improve power load transient response. Modeling and design approaches are validated by test circuit simulations, demonstrating stable operations using current mode control under constant power loads, and improved power step load transient response based on load current feedforward. A buck/boost and LDO series architecture is proposed as the solution to address efficiency, linearity, noise and time mask requirements for the supplies supporting multi-standard, multi-band PAs. A monolithic integrated circuit (IC) has been designed and implemented in a standard 0.5 5V CMOS process for supplying the multi-mode PAs. The buck/boost converter with wide output range delivers the peak efficiency of 92%. The power LDO has 1-4 MHz bandwidth, to support the GSM/EDGE/WCDMA time mask requirements and the polar EDGE operation. The test chip consumes the quiescent current 1.1 mA, and it delivers maximum 5 W output

Power conversion techniques in nanometer CMOS for low-power applications

As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration

REGULATED TRANSFORMER RECTIFIER UNIT FOR MORE ELECTRIC AIRCRAFTS

The impending trends in the global demand of more-electric-aircrafts with higher efficiency, high power density, and high degree of compactness has opened up numerous opportunities in front of avionic industries to develop innovative power electronic interfaces. Traditionally, passive diode-bridge based transformer rectifier units (TRU) have been used to generate a DC voltage supply from variable frequency and variable voltage AC power out of the turbo generators. These topologies suffer from bulky and heavy low-frequency transformer size, lack of DC-link voltage regulation flexibility, high degree of harmonic contents in the input currents, and additional cooling arrangement requirements. This PhD research proposes an alternative approach to replace TRUs by actively controlled Regulated Transformer Rectifier Units (RTRUs) employing the advantages of emerging wide band gap (WBG) semiconductor technology. The proposed RTRU utilizing Silicon Carbide (SiC) power devices is composed of a three-phase active boost power factor correction (PFC) rectifier followed by an isolated phase-shifted full bridge (PSFB) DC-DC converter. Various innovative control algorithms for wide-range input frequency operation, ultra-compact EMI filter design methodology, DC link capacitor reduction approach and novel start-up schemes are proposed in order to improve power quality and transient dynamics and to enhance power density of the integrated converter system. Furthermore, a variable switching frequency control algorithm of PSFB DC-DC converter has been proposed for tracking maximum conversion efficiency at all feasible operating conditions. In addition, an innovative methodology engaging multi-objective optimization for designing electromagnetic interference (EMI) filter stage with minimized volume subjected to the reactive power constraints is analyzed and validated experimentally. For proof-of-concept verifications, three different conversion stages i.e. EMI filter, three-phase boost PFC and PSFB converter are individually developed and tested with upto 6kW (continuous) / 10kW (peak) power rating, which can interface a variable input voltage (190V-240V AC RMS) variable frequency (360Hz – 800Hz) three-phase AC excitation source, emulating the airplane turbo generator and provide an AC RMS voltage of 190V to 260V. According to the experimental measurements, total harmonic distortion (THD) as low as 4.3% and an output voltage ripple of ±1% are achieved at rated output power. The proposed SiC based RTRU prototype is ~8% more efficient and ~50% lighter than state-of-the art TRU technologies

Extreme Temperature Switch Mode Power Supply Based on Vee-square Control Using Silicon Carbide, Silicon on Sapphire, Hybrid Technology

Switch mode power supplies, commonly known as SMPS are basic building blocks of the electronic systems. SMPS performs power regulation by accepting a raw input voltage and transforming it to required voltage at output with desired characteristics. Electronic systems used in applications such as deep well oil drilling, geothermal wells and deep space explorations is expected to operate under extremely harsh conditions like elevated temperature, high pressure and radiation prone environments. To support the onboard electronics in these applications, SMPS capable of operating at extreme temperatures are of high interest.This research work deals with the design and development of a switch mode power supply capable of operating over the temperature range of 300 degree centigrade (�C). Silicon carbide field effect transistors are used as power devices in the design to tolerate these extreme high ambient temperatures without compromising power handling capability. The simplest yet robust vee square control architecture is adopted for control mechanism. The control electronics are implemented as an integrated circuit in 0.5 �m silicon on sapphire process. The supporting components like high temperature tolerant inductors and capacitors are identified by evaluating various samples at elevated temperature. This is the first demonstration of SMPS capable of operating at 275�C as a standalone component. Also for the first time, a gate drive mechanism based on planar transformer architecture is studied and presented for high temperature operation. A low cost packaging technique suited for harsh environment operation is proposed based on gold on aluminum nitride thin film technology. The basic analog building blocks of the system, such as comparator, voltage reference and rail-to-rail amplifiers are made available in discrete packages for use at temperatures above 275�C. A SMPS prototype on a 1.8 square inches substrate is developed and tested. Test results indicate that the system is capable of operating continuously at 275�C for extended period of time, providing the desired performance characteristics.School of Electrical & Computer Engineerin

MODELING AND CONTROL OF DIRECT-CONVERSION HYBRID SWITCHED-CAPACITOR DC-DC CONVERTERS

Efficient power delivery is increasingly important in modern computing, communications, consumer and other electronic systems, due to the high power demand and thermal concerns accompanied by performance advancements and tight packaging. In pursuit of high efficiency, small physical volume, and flexible regulation, hybrid switched-capacitor topologies have emerged as promising candidates for such applications. By incorporating both capacitors and inductors as energy storage elements, hybrid topologies achieve high power density while still maintaining soft charging and efficient regulation characteristics. However, challenges exist in the hybrid approach. In terms of reliability, each flying capacitor should be maintained at a nominal `balanced\u27 voltage for robust operation (especially during transients and startup), complicating the control system design. In terms of implementation, switching devices in hybrid converters often need complex gate driving circuits which add cost, area, and power consumption. This dissertation explores techniques that help to mitigate the aforementioned challenges. A discrete-time state space model is derived by treating the hybrid converter as two subsystems, the switched-capacitor stage and the output filter stage. This model is then used to design an estimator that extracts all flying capacitor voltages from the measurement of a single node. The controllability and observability of the switched-capacitor stage reveal the fundamental cause of imbalance at certain conversion ratios. A new switching sequence, the modified phase-shifted pulse width modulation, is developed to enable natural balance in originally imbalanced scenarios. Based on the model, a novel control algorithm, constant switch stress control, is proposed to achieve both output voltage regulation and active balance with fast dynamics. Finally, the design technique and test result of an integrated hybrid switched-capacitor converter are reported. A proposed gate driving strategy eliminates the need for external driving supplies and reduces the bootstrap capacitor area. On-chip mixed signal control ensures fast balancing dynamics and makes hard startup tolerable. This prototype achieves 96.9\% peak efficiency at 5V:1.2V conversion and a startup time of 12$\mu s$, which is over 100 times faster than the closest prior art. With the modeling, control, and design techniques introduced in this dissertation, the application of hybrid switched-capacitor converters may be extended to scenarios that were previously challenging for them, allowing enhanced performance compared to using traditional topologies. For problems that may require future attention, this dissertation also points to possible directions for further improvements

Design and test of digitally-controlled power management IPs in advanced CMOS technologies

Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35 m: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.Owing to the development of modern semiconductor technology, it is possible to implement a digital controller for low-power high switching frequency DC-DC power converter in FPGA and ASIC. This thesis is intended to propose digital controllers with high performance, low power consumption and simple implementation architecture. Besides existing digital control-laws, such as PID, RST, tri-mode and sliding-mode (SM), a novel digital control-law, direct control with dual-state-variable prediction (DDP control), for the buck converter is proposed based on the principle of predictive control. Compared to traditional current-mode predictive control, the predictions of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal. DDP control exhibits very high dynamic transient performances under both load variations and reference changes. Experimental results in FPGA verify the performances at switching frequency up to 4MHz. For the boost converter exhibiting more serious nonlinearity, linear PID and nonlinear SM controllers are designed and implemented in FPGA to verify the performances. A digital control requires a DPWM. Sigma-Delta DPWM is therefore a good candidate regarding the implementation complexity and performances. An idle-tone free condition for Sigma-Delta DPWM is considered to reduce the inherent tone-noise under DC-excitation compared to the classic approach. A guideline for Sigma-Delta DPWM helps to satisfy proposed condition. In addition, an 1-1 MASH Sigma-Delta DPWM with a feasible dither generation module is proposed to further restrain the idle-tone effect without deteriorating the closed-loop stability as well as to preserve a reasonable cost in hardware resources. The FPGA-based experimental results verify the performances of proposed DPWM in steady-state and transient-state. Two ASICs in 0.35 m CMOS process are implemented including the tri-mode controller for buck converter and the PID and SM controllers for the buck and boost converters respectively. The lab-scale tests are designed to lead to a power assessment model suggesting feasible applications. For the tri-mode controller, the measured power consumption is only 24.56mW/MHz when the time ratio of stand-by operation mode is 0.7. As specific power optimization strategies in RTL and system-level are applied to the latter chip, the measured power consumptions of the SM controllers for buck converter and boost converter are 4.46mW/MHz and 4.79mW/MHz respectively. The power consumption is foreseen as less than 1mW/MHz when the process scales down to nanometer technologies based on the power-scaling model. Compared to the state-of-the-art analog counterpart, the prototype ICs are proven to achieve comparable or even higher power efficiency for low-to-medium power applications with the benefit of better accuracy and better flexibility.VILLEURBANNE-DOC'INSA-Bib. elec. (692669901) / SudocSudocFranceF