DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH

Static and dynamic nonlinearity compensation techniques for high performance current-steering digital-to-analog converters

High-speed high-accuracy digital-to-analog converters (DACs) are the crucial building blocks for many signal processing and telecommunication systems. The current-steering architecture is extensively used for these applications. With different decoding schemes--binary-weighted, unary-coded, and segment-coded, current-steering DACs are realized by groups of matched current sources. Their performance is limited by many nonlinear mechanisms such as random mismatch errors, gradient effect, code and voltage dependence of finite output impedance, nonlinear settling time, charge injection, and switch timing errors. In this thesis, two nonlinearity compensation techniques are presented to improve the overall performance of the current-steering DACs. The first design technique is a novel digital calibration technique--complete-folding, which effectively compensates the random mismatch errors by selectively regrouping current sources into a fully binary-weighted array based on current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes complete-folding calibration suitable for DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to the DAC without using any calibration. Additional results also show that this new calibration technique has the superior performance in compensating random mismatch errors as compared to state-of-the-art. The second design technique is a novel output impedance linearization technique that very effectively reduces the code and voltage dependence of finite output impedance. The linearization is achieved by using a small DAC switched with control signals opposite to those for the main DAC. The area and power overhead is less than 5% of the main DAC. Simulation results with a 14-bit segmented current-steering DAC in standard 0.18μm CMOS process show that the DAC\u27s integral nonlinearity (INL) due to finite output impedance is improved by almost 5 bits. Additional results show that this technique is very robust to random mismatch errors. Moreover, not only the static linearity is improved, but most importantly there is a large dynamic linearity enhancement by output impedance linearization. Simulation results show that spurious-free dynamic range (SFDR) can be improved by almost 30 dB at the low signal frequencies and more than 8 dB for the high signal frequencies up to Nyquist rate while sampling at 500MS/s

Smart and high-performance digital-to-analog converters with dynamic-mismatch mapping

The trends of advanced communication systems, such as the high data rate in multi-channel base-stations and digital IF conversion in software-defined radios, have caused a continuously increasing demand for high performance interface circuits between the analog and the digital domain. A Digital-to-Analog converter (DAC) is such an interface circuit in the transmitter path. High bandwidth, high linearity and low noise are the main design challenges in high performance DACs. Current-steering is the most suitable architecture to meet these performance requirements. The aim of this thesis is to develop design techniques for high-speed high-performance Nyquist current-steering DACs, especially for the design of DACs with high dynamic performance, e.g. high linearity and low noise. The thesis starts with an introduction to DACs in chapter 2. The function in time/frequency domain, performance specifications, architectures and physical implementations of DACs are brie y discussed. Benchmarks of state-of-the-art published Nyquist DACs are also given. Chapter 3 analyzes performance limitations by various error sources in Nyquist current-steering DACs. The outcome shows that in the frequency range of DC to hundreds of MHz, mismatch errors, i.e. amplitude and timing errors, dominate the DAC linearity. Moreover, as frequencies increase, the effect of timing errors becomes more and more dominant over that of amplitude errors. Two new parameters, i.e. dynamic-INL and dynamic-DNL, are proposed to evaluate the matching of current cells. Compared to the traditional static-INL/DNL, the dynamic-INL/DNL can describe the matching between current cells more accurately and completely. By reducing the dynamic-INL/DNL, the non-linearities caused by all mismatch errors can be reduced. Therefore, both the DAC static and dynamic performance can be improved. The dynamic-INL/DNL are frequency-dependent parameters based on the measurement modulation frequency fm. This fm determines the weight between amplitude and timing errors in the dynamic-INL/DNL. Actually, this gives a freedom to optimize the DAC performance for different applications, e.g. low fm for low frequency applications and high fm for high frequency applications. Chapter 4 summarizes the existing design techniques for intrinsic and smart DACs. Due to technology limitations, it is diffcult to reduce the mismatch errors just by intrinsic DAC design with reasonable chip area and power consumption. Therefore, calibration techniques are required. An intrinsic DAC with calibration is called a smart DAC. Existing analog calibration techniques mainly focus on current source calibration, so that the amplitude error can be reduced. Dynamic element matching is a kind of digital calibration technique. It can reduce the non-linearities caused by all mismatch errors, but at the cost of an increased noise oor. Mapping is another kind of digital calibration technique and will not increase the noise. Mapping, as a highly digitized calibration technique, has many advantages. Since it corrects the error effects in the digital domain, the DAC analog core can be made clean and compact, which reduces the parasitics and the interference generated in the analog part. Traditional mapping is static-mismatch mapping, i.e. mapping only for amplitude errors, which many publications have already addressed on. Several concepts have also been proposed on mapping for timing errors. However, just mapping for amplitude or timing error is not enough to guarantee a good performance. This work focuses on developing mapping techniques which can correct both amplitude and timing errors at the same time. Chapter 5 introduces a novel mapping technique, called dynamic-mismatch mapping (DMM). By modulating current cells as square-wave outputs and measuring the dynamic-mismatch errors as vectors, DMM optimizes the switching sequence of current cells based on dynamic-mismatch error cancelation such that the dynamic-INL can be reduced. After reducing the dynamic-INL, the non-linearities caused by both amplitude and timing errors can be significantly reduced in the whole Nyquist band, which is confirmed by Matlab behavioral-level Monte-Carlo simulations. Compared to traditional static-mismatch mapping (SMM), DMM can reduce the non-linearities caused by both amplitude and timing errors. Compared to dynamic element matching (DEM), DMM does not increase the noise floor. The dynamic-mismatch error has to be accurately measured in order to gain the maximal benefit from DMM. An on-chip dynamic-mismatch error sensor based on a zero-IF receiver is proposed in chapter 6. This sensor is especially designed for low 1/f noise since the signal is directly down-converted to DC. Its signal transfer function and noise analysis are also given and con??rmed by transistor-level simulations. Chapter 7 gives a design example of a 14-bit current-steering DAC in 0.14mum CMOS technology. The DAC can be configured in an intrinsic-DAC mode or a smart-DAC mode. In the intrinsic-DAC mode, the 14-bit 650MS/s intrinsic DAC core achieves a performance of SFDR>65dBc across the whole 325MHz Nyquist band. In the smart-DAC mode, compared to the intrinsic DAC performance, DMM improves the DAC performance in the whole Nyquist band, providing at least 5dB linearity improvement at 200MS/s and without increasing the noise oor. This 14-bit 200MS/s smart DAC with DMM achieves a performance of SFDR>78dBc, IM

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration