8 research outputs found
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Energy-efficient data converter design in scaled CMOS technology
Data converters bridge the physical and digital worlds. They have been the crucial building blocks in modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT) and 5G communications. The applications raise energy-efficiency requirements for both low-speed and high-speed converters since they are widely deployed in wireless sensor nodes and portable devices. To explore the solutions, the author worked on three directions: 1) techniques to improve the efficiency of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and results in higher noise. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain, thereby reducing noise and offset. Besides, statistical estimation and loading switching techniques are combined to further improve energy efficiency. A 40-nm CMOS prototype achieves a Walden FoM of 1.5 fJ/conversion-step while operating at 100-kS/s from a 0.5-V supply. To further improve the energy-efficiency of the comparator, a novel dynamic pre-amp is proposed. By using an inverter-based input pair powered by a floating reservoir capacitor, the pre-amp realizes both current reuse and dynamic bias, thereby significantly boosting g [subscript m] /I [subscript D] and reducing noise. Moreover, it greatly reduces the influence of the input common-mode (CM) voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180-nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V supply, which represents greater than 7 times energy efficiency boost compared to that of a Strong-Arm (SA) latch. The second part of this dissertation focuses on high-speed data converter techniques. A 10-bit high-speed two-stage loop-unrolled SAR ADC is presented. To reduce the SAR logic delay and power, each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. To suppress the comparator offset mismatch induced non-linearity, a shared pre-amp are employed in the second fine stage, which is implemented by a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55-dB peak SNDR at 200-MS/s sampling rate without any calibration. A key limiting factor for the SAR ADC to simultaneously achieve high speed and high resolution is the reference ripple settling problem caused by DAC switching. Unlike prior techniques that aim to minimize the reference ripple which requires large reference buffer power or on-chip decoupling capacitance area, this work proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. The prototype 10-bit 120-MS/s SAR ADC is fabricated in 40-nm CMOS process and achieves an SNDR of 55 dB with only 3 pF reference decoupling capacitor. Finally, this dissertation also presents the design of an incremental time-domain two-step CDC. Unlike the classic two-step CDC, this work replaces the OTA-based active-RC integrator with a VCO-based integrator and performs time domain (TD) ΔΣ modulation. The VCO is mostly digital and consumes low power. Featuring the infinite DC gain in phase domain and intrinsic spatial phase quantization, this TDΔΣ enables a CDC design, achieving 85-dB SQNR by having only a 4-bit quantizer, a 1st-order loop and a low OSR of 15. The prototype fabricated in 40-nm CMOS achieves a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by greater than 2 times comparing to that of state-of-the-art CDCsElectrical and Computer Engineerin
Space Power
Appropriate directions for the applied research and technology programs that will develop space power systems for U.S. future space missions beyond 1995 are explored. Spacecraft power supplies; space stations, space power reactors, solar arrays, thermoelectric generators, energy storage, and communication satellites are among the topics discussed
Proceedings of the ECCOMAS Thematic Conference on Multibody Dynamics 2015
This volume contains the full papers accepted for presentation at the ECCOMAS Thematic Conference on Multibody Dynamics 2015 held in the Barcelona School of Industrial Engineering, Universitat Politècnica de Catalunya, on June 29 - July 2, 2015. The ECCOMAS Thematic Conference on Multibody Dynamics is an international meeting held once every two years in a European country. Continuing the very successful series of past conferences that have been organized in Lisbon (2003), Madrid (2005), Milan (2007), Warsaw (2009), Brussels (2011) and Zagreb (2013); this edition will once again serve as a meeting point for the international researchers, scientists and experts from academia, research laboratories and industry working in the area of multibody dynamics. Applications are related to many fields of contemporary engineering, such as vehicle and railway systems, aeronautical and space vehicles, robotic manipulators, mechatronic and autonomous systems, smart structures, biomechanical systems and nanotechnologies. The topics of the conference include, but are not restricted to: ● Formulations and Numerical Methods ● Efficient Methods and Real-Time Applications ● Flexible Multibody Dynamics ● Contact Dynamics and Constraints ● Multiphysics and Coupled Problems ● Control and Optimization ● Software Development and Computer Technology ● Aerospace and Maritime Applications ● Biomechanics ● Railroad Vehicle Dynamics ● Road Vehicle Dynamics ● Robotics ● Benchmark ProblemsPostprint (published version
Multibody dynamics 2015
This volume contains the full papers accepted for presentation at the ECCOMAS Thematic Conference on Multibody Dynamics 2015 held in the Barcelona School of Industrial Engineering, Universitat Politècnica de Catalunya, on June 29 - July 2, 2015. The ECCOMAS Thematic Conference on Multibody Dynamics is an international meeting held once every two years in a European country. Continuing the very successful series of past conferences that have been organized in Lisbon (2003), Madrid (2005), Milan (2007), Warsaw (2009), Brussels (2011) and Zagreb (2013); this edition will once again serve as a meeting point for the international researchers, scientists and experts from academia, research laboratories and industry working in the area of multibody dynamics. Applications are related to many fields of contemporary engineering, such as vehicle and railway systems, aeronautical and space vehicles, robotic manipulators, mechatronic and autonomous systems, smart structures, biomechanical systems and nanotechnologies. The topics of the conference include, but are not restricted to: Formulations and Numerical Methods, Efficient Methods and Real-Time Applications, Flexible Multibody Dynamics, Contact Dynamics and Constraints, Multiphysics and Coupled Problems, Control and Optimization, Software Development and Computer Technology, Aerospace and Maritime Applications, Biomechanics, Railroad Vehicle Dynamics, Road Vehicle Dynamics, Robotics, Benchmark Problems. The conference is organized by the Department of Mechanical Engineering of the Universitat Politècnica de Catalunya (UPC) in Barcelona. The organizers would like to thank the authors for submitting their contributions, the keynote lecturers for accepting the invitation and for the quality of their talks, the awards and scientific committees for their support to the organization of the conference, and finally the topic organizers for reviewing all extended abstracts and selecting the awards nominees.Postprint (published version
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Design techniques for ultra-low-power sensor interface circuits and systems in nano-scale CMOS technologies
In recent decades, the internet of things (IoT) has been sprout, resulting from the improvement of the circuit design and manufacturing techniques. Moreover, the emerging of 5G technologies further enhances its growth. Autonomous wireless sensors and their networks have been one of the most prevailing and important research topics for the past decades. Although researchers have been pushing the state-of-the-art of sensor readout to have higher and higher power and area efficiency, the results turn out to be insufficient to meet the modern requirements, especially considering the number of sensors is dramatically growing and a large portion of them are battery-less devices. Thus, maintaining a high resolution and low noise while achieving a high power and area efficiency has been one of the major challenges for sensor readout circuit designs in recent years. This thesis proposes several novel power- and area-saving techniques for the fundamental building blocks: 1) the inverter-stacking technique; and 2) the tail-less inverter-stacking technique for LNA; 3) the CT-SAR-assisted two-step SAR ADC with kT/C noise attenuated. The first work presents a highly power-efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves 6-time current reuse, thereby significantly boosting the transconductance and lowering noise but without increasing the current consumption. A novel biasing scheme is devised to ensure robust operation under 1 V supply. A prototype in 180 nm CMOS has 5.5 μV [subscript rms] noise within 10 kHz BW while consuming only 0.25 μW power, leading to a noise efficiency factor (NEF) of 1.07, which is the best among reported amplifiers. The second work presents a low-noise capacitively-coupled instrumentation amplifier, featuring the better-than-bipolar power efficiency. The tail-less structure removes the tail current source, reducing the supply voltage to be 0.6 V, and thus significantly reducing the power consumption. Compared with other recently reported front-end amplifiers, it achieves the best trade-off between power consumption and input-referred noise (IRN). AC-coupling and current mode biased are employed to enhance its PVT robustness.f In addition, several other design techniques are used, including AC coupling with optimized gain allocation-based ripple reduction, CM-pre-filtering based CMRR enhancement. The prototype fabricated in 180-nm CMOS process achieved an integrated input-referred rms noise of 1.38 μV [subscript rms] within an 8-kHz bandwidth. With one global 0.6-V supply voltage, the prototype consumes 2.7-μW of total power, leading to a PEF of 0.96. The peak CMRR and PSRR are measured to be 84 dB and 78 dB, respectively, which validates the performance enhancement techniques with the pseudo-differential input stage. The third work presents a two-step analog-to-digital converter (ADC) that operates its 1st-stage successive approximation register (SAR) ADC in the continuous-time (CT) domain. It avoids the front-end sample-and-hold (S/H) circuit and its associated sampling noise. Hence, the proposed ADC allows the input capacitor size to be substantially reduced without incurring large sampling noise penalty. With input AC coupling, the 1st-stage CT SAR can simultaneously perform input tracking and SAR quantization. Its conversion error is minimized by accelerating the SAR speed and providing redundancy. A floating inverter-based (FIB) dynamic amplifier (DA) is used as the inter-stage amplifier and acts as a low-pass filter for the 1st-stage residue. To verify the proposed techniques, a 13-bit prototype ADC is built in 40nm CMOS process. Its input capacitor is only 120 fF, which is over 20 times smaller than what would be needed in a classic Nyquist ADC with the S/H circuit. Operating at 2 MS/s, it achieves 72-dB SNDR at the Nyquist rate while consuming only 25 μW of power and 0.01 mm² of area.Electrical and Computer Engineerin