Active C4 electrodes for local field potential recording applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.R01 NS072385 - NINDS NIH HHS; 1R01 NS072385 - NINDS NIH HH

A CMOS low pass filter for soc lock-in-based measurement devices

This paper presents a fully integrated Gm–C low pass ¿lter (LPF) based on a current ¿steering Gm reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm2 /pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels

Current-efficient preamplifier architecture for CMRR sensitive neural recording applications

Este trabajo fue parcialmente financiado por CSIC (Comisión Sectorial de Investigación Científica, Uruguay), ANII (Agencia Nacional de Investigación e Innovación, Uruguay) y CAP (Comisión Académica de Posgrado, Uruguay).There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting invivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5 μm CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88 μVrms, the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system

Area- and Energy- Efficient Modular Circuit Architecture for 1,024-Channel Parallel Neural Recording Microsystem.

This research focuses to develop system architectures and associated electronic circuits for a next generation neuroscience research tool, a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in recordings. First, a modular 128-channel Δ-ΔΣ AFE using the spectrum shaping has been designed and fabricated to propose an area-and energy efficient solution for neural recording AFEs. The AFE achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems. It also features power and area consumption of 3.05 µW and 0.05 mm2 per channel, respectively while exhibiting 63.3 dB signal-to-noise ratio with 3.02 µVrms input referred noise. Second, an on-chip mixed signal neural signal compressor was built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: LFP and AP without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 µW that is about 1/9 of 107.5 µW without the compression. Third, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 µW that is relevant power most of the multi-channel neural recording systems consume. The dc-to-dc converter occupies 0.375 mm2 of area which is less than 1/20 of the area the first prototype consumes (8.64 mm2).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133244/1/sungyun_1.pd

Time Multiplexed Active Neural Probe with 678 Parallel Recording Sites

We present a high density CMOS neural probe with active electrodes (pixels), consisting of dedicated in-situ circuits for signal source amplification. The complete probe contains 1356 neuron size (20x20 μm2) pixels densely packed on a 50 μm thick, 100 μm wide and 8 mm long shank. It allows simultaneous highperformance recording from 678 electrodes and a possibility to simultaneously observe all of the 1356 electrodes with increased noise. This considerably surpasses the state of the art active neural probes in electrode count and flexibility. The measured action potential band noise is 12.4 μVrms, with just 3 μW power dissipation per electrode amplifier and 45 μW per channel (including data transmission)

Integrated circuit design for implantable neural interfaces

Progress in microfabrication technology has opened the way for new possibilities in neuroscience and medicine. Chronic, biocompatible brain implants with recording and stimulation capabilities provided by embedded electronics have been successfully demonstrated. However, more ambitious applications call for improvements in every aspect of existing implementations. This thesis proposes two prototypes that advance the field in significant ways. The first prototype is a neural recording front-end with spectral selectivity capabilities that implements a design strategy that leads to the lowest reported power consumption as compared to the state of the art. The second one is a bidirectional front-end for closed-loop neuromodulation that accounts for self-interference and impedance mismatch thus enabling simultaneous recording and stimulation. The design process and experimental verification of both prototypes is presented herein

A Multimodal Neural Activity Readout Integrated Circuit for Recording Fluorescence and Electrical Signals

Monitoring the electrical neural signals is an important method for understanding the neuronal mechanism. In particular, in order to perform a cell-type-specific study, it is necessary to observe the concentration of calcium ions using fluorescent indicators in addition to measuring the electrical neural signal. This paper presents a multimodal multichannel neural activity readout integrated circuit that can perform not only electrical neural recording but also fluorescence recording of neural activity for the cell-type-specific study of heterogeneous neuronal cell populations. For monitoring the calcium ions, the photodiode generates the current according to the fluorescence expressed by the reaction between the genetically encoded calcium indicators and calcium ions. The time-based fluorescence recording circuit then records the photodiode current. The electrical neural signal captured by the microelectrode is recorded through the low-noise amplifier, variable gain amplifier, and analog-to-digital converter. The proposed integrated circuit is fabricated in a 1-poly 6-metal (1P6M) 0.18- ??m CMOS process. The fluorescence recording circuit achieves a recording range of 81 dB (75 pA to 860 nA) and consumes a power of 724 nW/channel. The electrical recording circuit achieves an input-referred noise of 2.7 ??Vrms over the bandwidth of 10 kHz, while consuming the power of 4.9 ??W /channel. The functionality of the proposed circuits is verified through the in vivo and in vitro experiments. Compared to the conventional neuroscience tools, which consist of bulky off-chip components, this neural interface is implemented in a compact size to perform multimodal neural recording while consuming low power

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /

Noise Analysis for Performance Evaluation of Biopotential Recording Front-Ends

Noise efficiency factor (NEF) and power efficiency factor (PEF) are widely used as the figure of merit to quantify the performance of biopotential recording front-ends. NEF and PEF are discussed from the noise analysis to the trend survey. To provide a comprehensive performance comparison of the front-ends, the performance mapping is developed using the design parameters of the technology node, NEF, PEF, |PEF - NEF|, and supply voltage. Using |PEF - NEF| provides how well a front-end balances between current-noise efficiency and power-noise efficiency, in other words, how biased a front-end is between current- and power-noise efficiencies. Also, the performance mappings of different front-end architectures are presented.Comment: 16 pages, 8 figure

Wearable electroencephalography for long-term monitoring and diagnostic purposes

Truly Wearable EEG (WEEG) can be considered as the future of ambulatory EEG units, which are the current standard for long-term EEG monitoring. Replacing these short lifetime, bulky units with long-lasting, miniature and wearable devices that can be easily worn by patients will result in more EEG data being collected for extended monitoring periods. This thesis presents three new fabricated systems, in the form of Application Specific Integrated Circuits (ASICs), to aid the diagnosis of epilepsy and sleep disorders by detecting specific clinically important EEG events on the sensor node, while discarding background activity. The power consumption of the WEEG monitoring device incorporating these systems can be reduced since the transmitter, which is the dominating element in terms of power consumption, will only become active based on the output of these systems. Candidate interictal activity is identified by the developed analog-based interictal spike selection system-on-chip (SoC), using an approximation of the Continuous Wavelet Transform (CWT), as a bandpass filter, and thresholding. The spike selection SoC is fabricated in a 0.35 μm CMOS process and consumes 950 nW. Experimental results reveal that the SoC is able to identify 87% of interictal spikes correctly while only transmitting 45% of the data. Sections of EEG data containing likely ictal activity are detected by an analog seizure selection SoC using the low complexity line length feature. This SoC is fabricated in a 0.18 μm CMOS technology and consumes 1.14 μW. Based on experimental results, the fabricated SoC is able to correctly detect 83% of seizure episodes while transmitting 52% of the overall EEG data. A single-channel analog-based sleep spindle detection SoC is developed to aid the diagnosis of sleep disorders by detecting sleep spindles, which are characteristic events of sleep. The system identifies spindle events by monitoring abrupt changes in the input EEG. An approximation of the median frequency calculation, incorporated as part of the system, allows for non-spindle activity incorrectly identified by the system as sleep spindles to be discarded. The sleep spindle detection SoC is fabricated in a 0.18 μm CMOS technology, consuming only 515 nW. The SoC achieves a sensitivity and specificity of 71.5% and 98% respectively.Open Acces