Applicability of Dickson Charge Pump in Energy Harvesting Systems: Experimental Validation of Energy Harvesting Charge Pump Model

Energy harvesting methods provide very low instantaneous power. Accordingly, available voltage levels are low and must be increased so that an energy harvesting method can be used as a power supply. One approach uses charge pumps to boost low AC voltage from energy harvester to a higher DC voltage. Characterized by very low output current and a wide span of operating frequencies, energy harvesting methods introduce a number of limitations to charge pump operation. This paper describes and models behavior of Dickson charge pump in energy harvesting applications. Proposed Energy Harvesting model is evaluated and compared with Standard and Tanzawa charge pump models and with measurement results. Based on the proposed model, the conditions that need to be satisfied so that a charge pump can reach maximum power point of energy harvesting system are defined. Parameter selection method optimized for maximum power point is presented and is experimentally validated

A 32 mV/69 mV input voltage booster based on a piezoelectric transformer for energy harvesting applications

This paper presents a novel method for battery-less circuit start-up from ultra-low voltage energy harvesting sources. The approach proposes for the first time the use of a Piezoelectric Transformer (PT) as the key component of a step-up oscillator. The proposed oscillator circuit is first modelled from a theoretical point of view and then validated experimentally with a commercial PT. The minimum achieved start-up voltage is about 69 mV, with no need for any external magnetic component. Hence, the presented system is compatible with the typical output voltages of thermoelectric generators (TEGs). Oscillation is achieved through a positive feedback coupling the PT with an inverter stage made up of JFETs. All the used components are in perspective compatible with microelectronic and MEMS technologies. In addition, in case the use of a ∼40 μH inductor is acceptable, the minimum start-up voltage becomes as low as about 32 mV

Nano-Power Integrated Circuits for Energy Harvesting

The energy harvesting research field has grown considerably in the last decade due to increasing interests in energy autonomous sensing systems, which require smart and efficient interfaces for extracting power from energy source and power management (PM) circuits. This thesis investigates the design trade-offs for minimizing the intrinsic power of PM circuits, in order to allow operation with very weak energy sources. For validation purposes, three different integrated power converter and PM circuits for energy harvesting applications are presented. They have been designed for nano-power operations and single-source converters can operate with input power lower than 1 μW. The first IC is a buck-boost converter for piezoelectric transducers (PZ) implementing Synchronous Electrical Charge Extraction (SECE), a non-linear energy extraction technique. Moreover, Residual Charge Inversion technique is exploited for extracting energy from PZ with weak and irregular excitations (i.e. lower voltage), and the implemented PM policy, named Two-Way Energy Storage, considerably reduces the start-up time of the converter, improving the overall conversion efficiency. The second proposed IC is a general-purpose buck-boost converter for low-voltage DC energy sources, up to 2.5 V. An ultra-low-power MPPT circuit has been designed in order to track variations of source power. Furthermore, a capacitive boost circuit has been included, allowing the converter start-up from a source voltage VDC0 = 223 mV. A nano-power programmable linear regulator is also included in order to provide a stable voltage to the load. The third IC implements an heterogeneous multisource buck-boost converter. It provides up to 9 independent input channels, of which 5 are specific for PZ (with SECE) and 4 for DC energy sources with MPPT. The inductor is shared among channels and an arbiter, designed with asynchronous logic to reduce the energy consumption, avoids simultaneous access to the buck-boost core, with a dynamic schedule based on source priority

Analysis and design of switched-capacitor DC-DC converters with discrete event models

Ph. D. Thesis.Switched-capacitor DC-DC converters (SCDDCs) play a critical role in low power integrated systems. The analysis and design processes of an SCDDC impact the performance and power efficiency of the whole system. Conventionally, researchers carry out the analysis and design processes by viewing SCDDCs as analogue circuits. Analogue attributes of an SCDDC, such as the charge flow current or the equivalent output impedance, have been studied in considerable detail for performance enhancement. However, in most existing work, less attention is paid to the analysis of discrete events (e.g. digital signal transitions) and the relationships between discrete events in SCDDCs. These discrete events and the relationships between discrete events also affect the performance of SCDDCs. Certain negative effects of SCDDCs such as leakage current are introduced by unhealthy discrete states. For example, MOS devices in an SCDDC could conduct undesirably under certain combinations of signals, resulting in reversion losses (a type of leakage in SCDDCs). However, existing work only use verbal reasoning and waveform descriptions when studying these discrete events, which may cause confusion and result in an informal design process consisting of intuitive design and backed up merely by validation based on natural language discussions and simulations. There is therefore a need for formalised methods to describe and analyse these discrete events which may facilitate systematic design techniques. This thesis presents a new method of analysing and designing SCDDCs using discrete event models. Discrete event models such as Petri nets and Signal Transition Graphs (STGs) are commonly used in asynchronous circuits to formally describe and analyse the relationships between discrete transitions. Modelling SCDDCs with discrete event models provides a formal way to describe the relations between discrete transitions in SCDDCs. These discrete event models can be used for analysis, verification and even design guidance for SCDDC design. The rich set of existing analysis methods and tools for discrete event models could be applied to SCDDCs, potentially improving the analysis and design flow for them. Moreover, since Petri nets and STGs are generally used to analyse and design asynchronous circuits, modelling and designing SCDDCs with STG models may additionally facilitate the incorporation of positive features of asynchronous circuits in SCDDCs (e.g. no clock skew). In this thesis, the relations between discrete events in SCDDCs are formally described with SC-STG (an extended STG targeting multi-voltage systems, to which SCDDCs belong), which avoids the potential confusion due to natural language and waveform descriptions. Then the concurrency and causality relations described in SC-STG model are extended to Petri nets, with which the presence of reversion losses can be formally determined and verified. Finally, based on the STG and Petri net models, a new design method for reversion-loss-free SCDDCs is proposed. In SCDDCs designed with the new method, reversion losses are entirely removed by introducing asynchronous controls, synthesised with the help of a software synthesis toolkit “Workcraft”. To demonstrate the analysis capabilities of the method, several cross-coupled voltage doublers (a type of SCDDC) are analysed and studied with discrete event models as examples in this thesis. To demonstrate the design capabilities of the method, a new reversion-loss-free cross-coupled voltage doubler is designed. The cross-coupled voltage doubler is widely used in low power integrated systems such as flash memories, LCD drivers and wireless energy harvesting systems. The proposed modelling method is potentially used in both research and industrial area of those applications for a formal and high-efficiency design proces

Microelectronic Design with Integrated Magnetic and Piezoelectric Structures

This thesis investigates the possibility of integrating the standard CMOS design process with additional microstructures enhancing circuit functionalities. More specifically, the thesis faces the problem of miniaturization of magnetic and piezoelectric devices mostly focused on the application field of EH (Energy Harvesting) systems and ultra-low power and ultra-low voltage systems. It shows all the most critical aspects which have to be taken into account during the design process of miniaturized inductors for PwrSoC (Power System on Chip) or transformers. Furthermore it shows that it is possible to optimize the inductance value and also performances by means of a proper choice of the size of the planar core or choosing a different layout shape such as a serpentine shape in place of the classic toroidal one. A new formula for the correct evaluation of the MPL (Magnetic Path Length) was also introduced. Concerning the piezoelectric counterpart, it is focused on the design and simulation of various MEMS PTs based on a SOI (Silicon on Insulator) structure with AlN (Alluminum Nitride) as active piezoelectric element, in perspective of having a SoC with embedded MEMS devices and circuitry. Furthermore it demonstrates for the first time the use of a PT (Piezoelectric Transformer) for ultra-low voltage EH applications. A new boost oscillator based on a discrete PZT (Lead Zirconate Titanate) PT instead of a MT (Magnetic Transformer) has been modelled and tested on a circuit made up by discrete devices, showing performances comparable to commercial solutions like the LTC3108 from Linear. Furthermore this novel boost oscillator has been designed in a 0.35μm technology by ST Microelectronics, showing better performances as intuitively expected by the developed mathematical model of the entire system