An Efficient and Cost Effective FPGA Based Implementation of the Viola-Jones Face Detection Algorithm

We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping

Embedded Smart Car Security System on Face Detection

In this proposed embedded car security system, FDS(Face Detection System) is used to detect the face of the driver and compare it with the predefined face. For example, in the night when the car’s owner is sleeping and someone theft the car then FDS obtains images by one tiny web camera which can be hidden easily in somewhere in the car. FDS compares the obtained image with the predefined images if the image doesn’t match, then the information is sent to the owner through MMS. So now owner can obtain the image of the thief in his mobile as well as he can trace the location through GPS. The location of the car as well as its speed can be displayed to the owner through SMS. So by using this system, owner can identify the thief image as well as the location of the car This system prototype is built on the base of one embedded platform in which one SoC named “SEP4020”(works at 100MHz) controls all the processes .Experimental results illuminate the validity of this car security system

FPGA-Based Portable Ultrasound Scanning System with Automatic Kidney Detection

Bedsides diagnosis using portable ultrasound scanning (PUS) offering comfortable diagnosis with various clinical advantages, in general, ultrasound scanners suffer from a poor signal-to-noise ratio, and physicians who operate the device at point-of-care may not be adequately trained to perform high level diagnosis. Such scenarios can be eradicated by incorporating ambient intelligence in PUS. In this paper, we propose an architecture for a PUS system, whose abilities include automated kidney detection in real time. Automated kidney detection is performed by training the Viola–Jones algorithm with a good set of kidney data consisting of diversified shapes and sizes. It is observed that the kidney detection algorithm delivers very good performance in terms of detection accuracy. The proposed PUS with kidney detection algorithm is implemented on a single Xilinx Kintex-7 FPGA, integrated with a Raspberry Pi ARM processor running at 900 MHz

Embedded Face Detection and Facial Expression Recognition

Face Detection has been applied in many fields such as surveillance, human machine interaction, entertainment and health care. Two main reasons for extensive attention on this typical research domain are: 1) a strong need for the face recognition system is obvious due to the widespread use of security, 2) face recognition is more user friendly and faster since it almost requests the users to do nothing. The system is based on ARM Cortex-A8 development board, including transplantation of Linux operating system, the development of drivers, detecting face by using face class Haar feature and Viola-Jones algorithm. In the paper, the face Detection system uses the AdaBoost algorithm to detect human face from the frame captured by the camera. The paper introduces the pros and cons between several popular images processing algorithm. Facial expression recognition system involves face detection and emotion feature interpretation, which consists of offline training and online test part. Active shape model (ASM) for facial feature node detection, optical flow for face tracking, support vector machine (SVM) for classification is applied in this research

Cascaded face detection using neural network ensembles

We propose a fast face detector using an efficient architecture based on a hierarchical cascade of neural network ensembles with which we achieve enhanced detection accuracy and efficiency. First, we propose a way to form a neural network ensemble by using a number of neural network classifiers, each of which is specialized in a subregion in the face-pattern space. These classifiers complement each other and, together, perform the detection task. Experimental results show that the proposed neural-network ensembles significantly improve the detection accuracy as compared to traditional neural-network-based techniques. Second, in order to reduce the total computation cost for the face detection, we organize the neural network ensembles in a pruning cascade. In this way, simpler and more efficient ensembles used at earlier stages in the cascade are able to reject a majority of nonface patterns in the image backgrounds, thereby significantly improving the overall detection efficiency while maintaining the detection accuracy. An important advantage of the new architecture is that it has a homogeneous structure so that it is suitable for very efficient implementation using programmable devices. Our proposed approach achieves one of the best detection accuracies in literature with significantly reduced training and detection cost

A characterization of visual feature recognition

technical reportNatural human interfaces are a key to realizing the dream of ubiquitous computing. This implies that embedded systems must be capable of sophisticated perception tasks. This paper analyzes the nature of a visual feature recognition workload. Visual feature recognition is a key component of a number of important applications, e.g. gesture based interfaces, lip tracking to augment speech recognition, smart cameras, automated surveillance systems, robotic vision, etc. Given the power sensitive nature of the embedded space and the natural conflict between low-power and high-performance implementations, a precise understanding of these algorithms is an important step developing efficient visual feature recognition applications for the embedded space. In particular, this work analyzes the performance characteristics of flesh toning, face detection and face recognition codes based on well known algorithms. We also show how the problem can be decomposed into a pipeline of filters that have efficient implementations as stream processors

Face detection hardware accelerator using C-based high-level synthesis

Research has shown that Field Programmable Gate Array (FPGA) based implementation of image processing system results in high computational speed and energy efficiency. However, FPGA design has relatively long development time compared to alternative implementation platforms, such as those based on Central Processing Unit, Graphical Processing Unit or Digital Signal Processor. Designing digital hardware at a higher level of abstraction is an effective way to shorten the development time. High-level synthesis (HLS) raises the abstraction level for designing digital circuit and translates a C-based description of the desired design into Hardware Descriptive Language. However, C-based HLS techniques are still lacking some maturity. In particular, existing works on applying C-based HLS to design hardware that accelerates window-based image processing algorithms are generally done in a trial and error manner, and usually results in non-optimal designs. Hence, there is a need for an effective procedure in applying C-based HLS that can lead to an optimized accelerator design. Therefore, the key contribution of this research is to present a systematic C-based HLS technique to be used in the design of hardware that accelerates image processing algorithm. The proposed C-based HLS design procedure is illustrated with a case study of the Sobel filter. The effectiveness of the proposed design technique is demonstrated by the case study of a Viola- Jones face detection accelerator targeted for implementation in FPGA. The proposed face detection hardware applies a pipelined architecture with task-level parallelism that allows concurrent execution on every sub-module. Experimental results show that the resulting accelerator module achieves a speed performance improvement of up to 12 times when compared to that of existing works. Tested on CMU+MIT database, the proposed accelerator achieves high detection accuracy of 88% and 46 false positives. Experimental results also show that the proposed design achieves up to 61 frames per second detection speed. This work demonstrates that the proposed Cbased HLS design methodology is effective for image processing hardware accelerator development

Thai Finger-Spelling Recognition Using a Cascaded Classifier Based on Histogram of Orientation Gradient Features

Hand posture recognition is an essential module in applications such as human-computer interaction (HCI), games, and sign language systems, in which performance and robustness are the primary requirements. In this paper, we proposed automatic classification to recognize 21 hand postures that represent letters in Thai finger-spelling based on Histogram of Orientation Gradient (HOG) feature (which is applied with more focus on the information within certain region of the image rather than each single pixel) and Adaptive Boost (i.e., AdaBoost) learning technique to select the best weak classifier and to construct a strong classifier that consists of several weak classifiers to be cascaded in detection architecture. We collected 21 static hand posture images from 10 subjects for testing and training in Thai letters finger-spelling. The parameters for the training process have been adjusted in three experiments, false positive rates (FPR), true positive rates (TPR), and number of training stages (N), to achieve the most suitable training model for each hand posture. All cascaded classifiers are loaded into the system simultaneously to classify different hand postures. A correlation coefficient is computed to distinguish the hand postures that are similar. The system achieves approximately 78% accuracy on average on all classifier experiments