Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters

This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successiveapproximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most powerefficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, ΔΣ modulators become more power-efficient. This is due to the intrinsic robustness of the ΔΣ modulation principle against circuit imperfections and nonidealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, ΔΣ ADCs result more area-efficient as well

Systematic Design Methodology for Successive – Approximation ADCs

Successive – Approximation ADCs are widely used in ultra – low – power applications. This paper describes a systematic design procedure for designing Successive – Approximation ADCs for biomedical sensor nodes. The proposed scheme is adopted in the design of a 12 bit 1 kS/s ADC. Implemented in 65 nm CMOS, the ADC consumes 354 nW at a sampling rate of 1 kS/s operating with 1.2 supply voltage. The achieved ENOB is 11.6, corresponding to a FoM of 114 fJ/conversion – step

Design of High Speed Split SAR ADC With Improved Linearity

Abstract: Recently low power Analog to Digital Converters(ADCs) have been developed for many energy constrained applications such as wireless sensor networks and bio-medical applications. Successive approximation register (SAR) ADC are good candidates for low power applications and widely used for low energy application due to its minimum analog blocks. The static linearity performance in terms of the integral nonlinearity and differential nonlinearity and the parasitic effects of the split DAC, are analyzed. A code-randomized calibration technique is done to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulation. Here the SAR ADC is designed in such a way that the control module completely control the splitting up of modules and the speed of operation is changed using low level input bits.A dedicated multiplexer can be used to minimize the capacitor array structure.The control module controls the clock signal and determines the time at which the analog signal should enter the SAR logic.On attaining control over the time of arrival of input signals the speed of conversion can be increased and power utilisation can be minimised

An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10^4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics

A Sub-mW Pulse-Based 5-bit Flash ADC with a Time-Domain Fully-Digital Reference Ladder

Journal article A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder: A Katic, Nikola; Cojbasic, Radisav; Schmid, Alexandre; Leblebici, Yusuf Published in: Microelectronics Journal (ISSN: 0026-2692), vol. 46, num. 12, p. 1343-1350 Oxford: Elsevier Sci Ltd, 2015 The concept of time-domain reference-ladder for the implementation of fully-digital flash-ADCs is proposed in this work. The complete reference ladder is implemented using only digital circuits. Based on this concept, a flash ADC is proposed and implemented in this work using digital circuits, one comparator and a customized sample-and-ramp circuit. An unconventional time-to-digital conversion (TDC) technique is introduced which performs the complete conversion within a single clock cycle. The measurement results show that the proposed 5-bit converter achieves an 80 MHz sampling rate while consuming 900 mu W of power from the 1.8 V supply voltage. The prototype ADC is developed in a 180 nm standard CMOS technology and achieves the power efficiency of 445 fJ/conversion which is comparable to many existing state-of-the-art flash ADCs. The measured performance is achieved without any design optimization or circuit calibration techniques confirming the promising benefits of the proposed topology. Thanks to the fully-digital structure, the circuit enables a robust and compact implementation which is very convenient for interleaving and beneficial for many potential applications

High speed – energy efficient successive approximation analog to digital converter using tri-level switching

This thesis reports issues and design methods used to achieve high-speed and high-resolution Successive Approximation Register analog to digital converters (SAR ADCs). A major drawback of this technique relates to the mismatch in the binary ratios of capacitors which causes nonlinearity. Another issue is the use of large capacitors due to nonlinear effect of parasitic capacitance. Nonlinear effect of capacitor mismatch is investigated in this thesis. Based on the analysis, a new Tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over conventional SAR ADC, which is the lowest compared to the previously reported schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% compared with the conventional SAR architecture. A new correction method to solve metastability error of comparator based on a novel design approach is proposed which reduces the required settling time about 1.1τ for each conversion cycle. Based on the above proposed methods two SAR ADCs: an 8-bit SAR ADC with 50MS/sec sampling rate, and a 10-bit SAR split ADC with 70 MS/sec sampling rate have been designed in 0.18μm Silterra complementary metal oxide semiconductor (CMOS) technology process which works at 1.2V supply voltage and input voltage of 2.4Vp-p. The 8-bit ADC digitizes 25MHz input signal with 48.16dB signal to noise and distortion ratio (SNDR) and 52.41dB spurious free dynamic range (SFDR) while consuming about 589μW. The figure of merit (FOM) of this ADC is 56.65 fJ/conv-step. The post layout of the 10-bit ADC with 1MHz input frequency produces SNDR, SFDR and effective number of bits (ENOB) of 57.1dB, 64.05dB and 9.17Bit, respectively, while its DNL and INL are -0.9/+2.8 least significant bit (LSB) and -2.5/+2.7 LSB, respectively. The total power consumption, including digital, analog and reference power, is 1.6mW. The FOM is 71.75fJ/conv. step

Energy aware ultra-low power SAR ADC in 180nm CMOS for biomedical application

Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by batteries, such as implantable biomedical devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. In this thesis four architectures of SAR ADC is implemented with different energy efficiency. In first architecture, conventional SAR ADC was designed in 180nm CMOS technology with a 1-V power supply and a 1-kS/s sampling rate for monitoring bio potential signals, the ADC achieves a signal-to-noise and distortion ratio of 57.16 dB and consumes 43 nW power, resulting in a figure of merit of 73 fJ/conversion-step. In second architecture, Split capacitor SAR ADC was designed in 180nm CMOS with same resolution and sampling speed