三次元集積回路におけるチップ間ノイズ結合のその場評価と解析手法に関する研究

博士（工学）神戸大

A DLL Based Test Solution for 3D ICs

Integrated circuits (ICs) are rapidly changing and vertical integration and packaging strategies have already become an important research topic. 2.5D and 3D IC integrations have obvious advantages over the conventional two dimensional IC implementations in performance, capacity, and power consumption. A passive Si interposer utilizing Through-Silicon via (TSV) technology is used for 2.5D IC integration. TSV is also the enabling technology for 3D IC integration. TSV manufacturing defects can affect the performance of stacked devices and reduce the yield. Manufacturing test methodologies for TSVs have to be developed to ensure fault-free devices. This thesis presents two test methods for TSVs in 2.5D and 3D ICs utilizing Delay-Locked Loop (DLL) modules. In the test method developed for TSVs in 2.5D ICs, a DLL is used to determine the propagation delay for fault detection. TSV faults in 3D ICs are detected through observation of the control voltage of a DLL. The proposed test methods present a robust performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLLs. 3D full-wave simulations are performed to extract circuit level models for TSVs and fragments of an interposer wires using HFSS simulation tools. The extracted TSV models are then used to perform circuit level simulations using ADS tools from Agilent. Simulation results indicate that the proposed test solution for TSVs can detect manufacturing defects affecting the TSV propagation delay

3D DfT architecture for pre-bond and post-bond testing

\u3cp\u3eProcess technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as post-bond stack testing of both partial and complete stacks. The architecture enables on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow flexible optimization of the 3D-SIC test flow. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1500 or IEEE Std 1149.1. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.\u3c/p\u3

Integrating specification and test requirements as constraints in verification strategies for 2D and 3D analog and mixed signal designs

Analog and Mixed Signal (AMS) designs are essential components of today’s modern Integrated Circuits (ICs) used in the interface between real world signals and the digital world. They present, however, significant verification challenges. Out-of-specification failures in these systems have steadily increased, and have reached record highs in recent years. Increasing design complexity, incomplete/wrong specifications (responsible for 47% of all non functional ICs) as well as additional challenges faced when testing these systems are obvious reasons. A particular example is the escalating impact of realistic test conditions with respect to physical (interface between the device under test (DUT) and the test instruments, input-signal conditions, input impedance, etc.), functional (noise, jitter) and environmental (temperature) constraints. Unfortunately, the impact of such constraints could result in a significant loss of performance and design failure even if the design itself was flawless. Current industrial verification methodologies, each addressing specific verification challenges, have been shown to be useful for detecting and eliminating design failures. Nevertheless, decreases in first pass silicon success rates illustrate the lack of cohesive, efficient techniques to allow a predictable verification process that leads to the highest possible confidence in the correctness of AMS designs. In this PhD thesis, we propose a constraint-driven verification methodology for monitoring specifications of AMS designs. The methodology is based on the early insertion of test(s) associated with each design specification. It exploits specific constraints introduced by these planned tests as well as by the specifications themselves, as they are extracted and used during the verification process, thus reducing the risk of costly errors caused by incomplete, ambiguous or missing details in the specification documents. To fully analyze the impact of these constraints on the overall AMS design behavior, we developed a two-phase algorithm that automatically integrates them into the AMS design behavioral model and performs the specifications monitoring in a Matlab simulation environment. The effectiveness of this methodology is demonstrated for two-dimensional (2D) and three-dimensional (3D) ICs. Our results show that our approach can predict out-of-specification failures, corner cases that were not covered using previous verification methodologies. On one hand, we show that specifications satisfied without specification and test-related constraints have failed in the presence of these additional constraints. On the other hand, we show that some specifications may degrade or even cannot be verified without adding specific specification and test-related constraints

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p>Dissertatio