Implementation of Input Oriented Dynamic Voltage and Frequency Scaling for Multiplier on FPGA

This paper presents an Implementation of Dynamic voltage and frequency scaling according to input data. In the conventional method the power supply is fixed and independent on workload, so, voltage and area will be consumed unnecessary .Paper proposes the approach which focuses on making system dynamic for low power digital multiplier on reconfigurable device FPGA (Spartan III). For making system Dynamic input workload should be known and scanning is used to detect range of input so system can adjust voltage and frequency. Control signal generated from scanning which can dynamically change voltage and frequency for low power consumption according to input data

32 BIT×32 BIT MULTIPRECISION RAZOR-BASED DYNAMIC VOLTAGE SCALING MULTIPLIER WITH OPERANDS SCHEDULER

In this paper, a 32×32-bit multi-precision multiplier is described. The multiprecision (MP) multiplier that incorporates the variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and MP operands scheduling are used to provide a variety of operating conditions. The proposed multi-precision multiplier enables voltage and frequency scaling for low power operation. The highly dynamic voltage and frequency scaling circuits can autonomously configure the multiplier to operate with the lowest possible voltage and frequency to achieve the lowest power consumption In Previous paper PLL is used for the frequency division method. If using PLL for frequency division its hardware complexity increases. To decrease the hardware complexity and also speed is an increase is done by software using some frequency division methods. The multiplier can either work as independent smallerprecision multipliers or work as parallel to perform higher-precision multiplications. To operate at the proper precision and frequency the user’s require to configure a dynamic voltage/frequency scaling management unit