Using positive feedback adiabatic logic to implement reversible Toffoli gates

A reversible, positive feedback adiabatic logic circuit is presented, which by implementing the universal Toffoli gate demonstrates that reversible logic circuits can be created and implemented using this adiabatic logic family. When compared to circuits with similar circuit structures that do not incorporate complete recovery logic, the use of reversible structures shows a reduction in energy losses by a mean of just under 63%

Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers

We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs

IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing

Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging from a simple buffer/inverter up to a 32-bit multiplier are explored and result in consistent energy savings, showing that IDPAL could be a viable candidate for a low-power circuit implementation. This work also shows an application of IDPAL to secure low-power circuits against power analysis attacks. It is often assumed that encryption algorithms are perfectly secure against attacks, however, most times attacks using side channels on the hardware implementation of an encryption operation are not investigated. Power analysis attacks are a subset of side channel attacks and can be implemented by measuring the power used by a circuit during an encryption operation in order to obtain secret information from the circuit under attack. Most of the previously proposed solutions for power analysis attacks use a large amount of power and are unsuitable for a low-power application. The almost-equal energy consumption for any given input in an IDPAL circuit suggests that this logic family is a good candidate for securing low-power circuits again power analysis attacks. Experimental results ranging from small circuits to large multipliers are performed and the power-analysis attack resistance of IDPAL is investigated. Results show that IDPAL circuits are not only low-power but also the most secure against power analysis attacks when compared to other adiabatic low-power circuits. Finally, a hybrid adiabatic-CMOS microprocessor design is presented. The proposed microprocessor uses IDPAL for the implementation of circuits with high switching activity (e.g. ALU) and CMOS logic for other circuits (e.g. memory, controller). An adiabatic-CMOS interface for transforming adiabatic signals to square-wave signals is presented and issues associated with a hybrid implementation and their solutions are also discussed

A Novel Power Analysis Attack Resilient Adiabatic Logic without Charge Sharing

In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn’t require any charge sharing between the output nodes of the gates. The proposed logic also removes the non-adiabatic losses (NAL) during the evaluation phase of the power-clock. We investigate and compare our proposed and the existing secure adiabatic logic across a range of “power-clock” frequencies on the basis of percentage Normalized Energy Deviation (%NED), percentage Normalized Standard Deviation(%NSD) and average energy dissipation. The pre-layout and post-layout simulation results show that our proposed logic exhibits the least value of %NED and %NSD in comparison to the existing secure adiabatic logic designs at the frequency ranging from 1MHz to 100MHz. Also, our proposed logic consumes the lowest energy

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications

On the whole existing secure adiabatic logic designs exhibit variations in current peaks and have asymmetric structures. However, asymmetric structure and variations in current peaks make the circuit vulnerable to Power Analysis Attacks (PAA). In this paper, we shall present a novel PAA resilient adiabatic logic which has a symmetric structure and exhibits the least variations in current peaks for basic gates as well as in 8-bit Montgomery multiplier. The proposed logic has been compared with two recently proposed secure adiabatic logic designs for operating frequencies ranging from 1MHz to 100MHz and power-supply scaling ranging from 0.6V to 1.8V. Simulation results of the gates show that our proposed logic exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) under the said frequency variations. All the 2-input gates that deploy the proposed logic dissipate nearly the same average energy within 0.2% of each other at all the frequencies simulated and thus, along with the dataindependence,gate-function-independence is achieved. The paper will also report on the energy dissipated by the proposed logic which approaches that of the existing logic designs as the output load capacitance is increased above 100fF. The simulation results of the 8-bit adiabatic Montgomery multiplier show that the proposed logic exhibits the least value of NED and NSD under the said frequency variations and power-supply scaling. Finally, the paper will report on the current waveform graphs for variations in current peaks under power-clock scaling

Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle

Power consumption has become a very serious concern with regard to the rapid technology of Internet of Things (IoT) devices. The IoT devices, such as sensor nodes, secure cryptographic devices, and medical implantable devices are general embedded systems that require low power and operate at low-frequency speed. Countless efforts have been done to reduce power consumption in complementary metal oxide semiconductors (CMOS) through supply voltage downscaling, reducing unnecessary clock activity, avoiding long path circuit topology, etc. Another circuit technique for low-power purpose is by employing adiabatic switching principle. The adiabatic switching is commonly used in minimizing energy loss during charging/discharging period at all nodes of the circuit. In this paper, a low-power adiabatic CMOS/FinFETs circuit for low-power secure logic application is presented. The circuit speed, power consumption, and other evaluation metrics indicating the circuit performances will be compared among the proposed circuits and other circuit topologies that are available in the literature

Performance-Driven Energy-Efficient VLSI.

Today, there are two prevalent platforms in VLSI systems: high-performance and ultra-low power. High-speed designs, usually operating at GHz level, provide the required computation abilities to systems but also consume a large amount of power; microprocessors and signal processing units are examples of this type of designs. For ultra-low power designs, voltage scaling methods are usually used to reduce power consumption and extend battery life. However, circuit delay in ultra-low power designs increases exponentially, as voltage is scaled below Vth, and subthreshold leakage energy also increases in a near-exponential fashion. Many methods have been proposed to address key design challenges on these two platforms, energy consumption in high-performance designs, and performance/reliability in ultra-low power designs. In this thesis, charge-recovery design is explored as a solution targeting both platforms to achieve increased energy efficiency over conventional CMOS designs without compromising performance or reliability. To improve performance while still achieving high energy efficiency for ultra-low power designs, we propose Subthreshold Boost Logic (SBL), a new circuit family that relies on charge-recovery design techniques to achieve order-of-magnitude improvements in operating frequencies, and achieve high energy efficiency compared to conventional subthreshold designs. To demonstrate the performance and energy efficiency of SBL, we present a 14-tap 8-bit finite-impulse response (FIR) filter test-chip fabricated in a 0.13µm process. With a single 0.27V supply, the test-chip achieves its most energy efficient operating point at 20MHz, consuming 15.57pJ per cycle with a recovery rate of 89% and a FoM equal to 17.37 nW/Tap/MHz/InBit/CoeffBit. To reduce energy consumption at multi-GHz level frequencies, we explore the application of resonant-clocking to the design of a 5-bit non-interleaved resonant-clock ash ADC with a sampling rate of 7GS/s. The ADC has been designed in a 65nm bulk CMOS process. An integrated 0.77nH inductor is used to resonate the entire clock distribution network to achieve energy efficient operation. Operating at 5.5GHz, the ADC consumes 28mW, yielding 396fJ per conversion step. The clock network accounts for 10.7% of total power and consumes 54% less energy over CV^2. By comparison, in a typical ash ADC design, 30% of total power is clock-related.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/89779/1/wsma_1.pd

Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations

Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the overhead of generation, scheduling, and routing of the signals. Thus, we present “Without Charge-Sharing Quasi-Adiabatic Logic”, WCS-QuAL which doesn't require any charge sharing inputs and completely removes the NAL. The pre-layout and post-layout simulation results of the gates show that WCS-QuAL exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) against all process corner variations at frequencies ranging from 1 MHz to 100 MHz. It also shows least variations in average energy dissipation at all five process corners. The simulation results show that the 8-bit Montgomery multiplier using WCS-QuAL exhibits the least value of NED and NSD at all the simulated frequencies and against power-supply scaling and dissipates the lowest energy at frequencies ranging from 20 MHz to 100 MHz

Robustness of Power Analysis Attack Resilient Adiabatic Logic: WCS-QuAL under PVT Variations

In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of % Normalized Energy Deviation (NED) and % Normalized Standard Deviation (NSD) at all simulated frequencies. Also, all 2-input gates using WCS-QuAL dissipate nearly equal energy for all possible input transitions. In addition, the energy dissipated by WCS-QuAL approaches to the energy dissipation of EESPFAL and SPGAL as the output load capacitance is increased above 100fF. To further evaluate and compare the performance, GF (24) bit-parallel multiplier was implemented as a design example. The impact of Process-Voltage-Temperature (PVT) variations, power supply scaling and technology on the performance of the three logic designs was investigated and compared. Simulation results show that WCS-QuAL passed the functionality test against PVT variations and can perform well against the power supply scaling (from 1.8V to 0.5V). It also exhibits the least value of %NED and %NSD against PVT variations and when the power supply is scaled down compared to EE-SPFAL and SPGAL. At lower technology, WCS-QuAL, shows more improvement in energy dissipation than EE-SPFAL