4 research outputs found
PALS: Distributed Gradient Clocking on Chip
Consider an arbitrary network of communicating modules on a chip, each
requiring a local signal telling it when to execute a computational step. There
are three common solutions to generating such a local clock signal: (i) by
deriving it from a single, central clock source, (ii) by local, free-running
oscillators, or (iii) by handshaking between neighboring modules. Conceptually,
each of these solutions is the result of a perceived dichotomy in which
(sub)systems are either clocked or asynchronous. We present a solution and its
implementation that lies between these extremes. Based on a distributed
gradient clock synchronization algorithm, we show a novel design providing
modules with local clocks, the frequency bounds of which are almost as good as
those of free-running oscillators, yet neighboring modules are guaranteed to
have a phase offset substantially smaller than one clock cycle. Concretely,
parameters obtained from a 15nm ASIC simulation running at 2GHz yield
mathematical worst-case bounds of 20ps on the phase offset for a
node grid network
Introducing KeyRing selfâtimed microarchitecture and timingâdriven design flow
ABSTRACT: A self-timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating
Design of a SRAM memory controller and interface for in-memory computing applications
Recently, neural networks have gained much attention, due to their high effectiveness. Their operation principle is based on massively parallel calculations, which possess a challenge for classical computing architectures, based on the Von Neumann principle, which uses separate memory and computing units. Due to low throughput of interconnections between these two systems (the so called Von-Neumann bottleneck) neural net-works cannot be effectively computed by these classical architectures. Therefore, many in-memory-computing architectures, where many computations are performed inside memory, have been recently proposed to solve this issue. In-memory-computing system provides efficient implementation of massively parallel computation. However, providing necessary weights of neural networks into the computing units poses challenges, as memory is typically too small to fit all weights and perform all computations at once. Yet, finding efficient ways of loading weights into this memory has not been extensively researched. For that reason, this thesis focuses on design of memory controller, that is used in in-memory-computing architecture for transferring weights into the under-lying memory. Specifically, several controller topologies are compared, and one selected design is simulated in the context of an in-memory computing matrix. In addition, this thesis provides an extensive theory background of IMC system, namely its variations, basic building blocks, advantages and disadvantages
Architectural Exploration of KeyRing Self-Timed Processors
RĂSUMĂ
Les derniĂšres dĂ©cennies ont vu lâaugmentation des performances des processeurs contraintes
par les limites imposĂ©es par la consommation dâĂ©nergie des systĂšmes Ă©lectroniques : des trĂšs
basses consommations requises pour les objets connectés, aux budgets de dépenses électriques
des serveurs, en passant par les limitations thermiques et la durée de vie des batteries des
appareils mobiles. Cette forte demande en processeurs efficients en énergie, couplée avec
les limitations de la rĂ©duction dâĂ©chelle des transistorsâqui ne permet plus dâamĂ©liorer les
performances Ă densitĂ© de puissance constanteâ, conduit les concepteurs de circuits intĂ©grĂ©s
Ă explorer de nouvelles microarchitectures permettant dâobtenir de meilleures performances
pour un budget Ă©nergĂ©tique donnĂ©. Cette thĂšse sâinscrit dans cette tendance en proposant
une nouvelle microarchitecture de processeur, appelĂ©e KeyRing, conçue avec lâintention de
rĂ©duire la consommation dâĂ©nergie des processeurs.
La frĂ©quence dâopĂ©ration des transistors dans les circuits intĂ©grĂ©s est proportionnelle Ă leur
consommation dynamique dâĂ©nergie. Par consĂ©quent, les techniques de conception permettant
de réduire dynamiquement le nombre de transistors en opération sont trÚs largement
adoptĂ©es pour amĂ©liorer lâefficience Ă©nergĂ©tique des processeurs. La technique de clock-gating
est particuliĂšrement usitĂ©e dans les circuits synchrones, car elle rĂ©duit lâimpact de lâhorloge
globale, qui est la principale source dâactivitĂ©. La microarchitecture KeyRing prĂ©sentĂ©e dans
cette thÚse utilise une méthode de synchronisation décentralisée et asynchrone pour réduire
lâactivitĂ© des circuits. Elle est dĂ©rivĂ©e du processeur AnARM, un processeur dĂ©veloppĂ© par
Octasic sur la base dâune microarchitecture asynchrone ad hoc. Bien quâil soit plus efficient
en Ă©nergie que des alternatives synchrones, le AnARM est essentiellement incompatible avec
les mĂ©thodes de synthĂšse et dâanalyse temporelle statique standards. De plus, sa technique
de conception ad hoc ne sâinscrit que partiellement dans les paradigmes de conceptions asynchrones.
Cette thÚse propose une approche rigoureuse pour définir les principes généraux
de cette technique de conception ad hoc, en faisant levier sur la littérature asynchrone. La
microarchitecture KeyRing qui en résulte est développée en association avec une méthode
de conception automatisĂ©e, qui permet de sâaffranchir des incompatibilitĂ©s natives existant
entre les outils de conception et les systÚmes asynchrones. La méthode proposée permet de
pleinement mettre Ă profit les flots de conception standards de lâindustrie microĂ©lectronique
pour réaliser la synthÚse et la vérification des circuits KeyRing. Cette thÚse propose également
des protocoles expérimentaux, dont le but est de renforcer la relation de causalité
entre la microarchitecture KeyRing et une réduction de la consommation énergétique des
processeurs, comparativement Ă des alternatives synchrones Ă©quivalentes.----------ABSTRACT
Over the last years, microprocessors have had to increase their performances while keeping
their power envelope within tight bounds, as dictated by the needs of various markets: from
the ultra-low power requirements of the IoT, to the electrical power consumption budget
in enterprise servers, by way of passive cooling and day-long battery life in mobile devices.
This high demand for power-efficient processors, coupled with the limitations of technology
scalingâwhich no longer provides improved performances at constant power densitiesâ, is
leading designers to explore new microarchitectures with the goal of pulling more performances
out of a fixed power budget. This work enters into this trend by proposing a new
processor microarchitecture, called KeyRing, having a low-power design intent.
The switching activity of integrated circuitsâi.e. transistors switching on and offâdirectly
affects their dynamic power consumption. Circuit-level design techniques such as clock-gating
are widely adopted as they dramatically reduce the impact of the global clock in synchronous
circuits, which constitutes the main source of switching activity. The KeyRing microarchitecture
presented in this work uses an asynchronous clocking scheme that relies on decentralized
synchronization mechanisms to reduce the switching activity of circuits. It is derived from
the AnARM, a power-efficient ARM processor developed by Octasic using an ad hoc asynchronous
microarchitecture. Although it delivers better power-efficiency than synchronous
alternatives, it is for the most part incompatible with standard timing-driven synthesis and
Static Timing Analysis (STA). In addition, its design style does not fit well within the existing
asynchronous design paradigms. This work lays the foundations for a more rigorous
definition of this rather unorthodox design style, using circuits and methods coming from the
asynchronous literature. The resulting KeyRing microarchitecture is developed in combination
with Electronic Design Automation (EDA) methods that alleviate incompatibility issues
related to ad hoc clocking, enabling timing-driven optimizations and verifications of KeyRing
circuits using industry-standard design flows. In addition to bridging the gap with standard
design practices, this work also proposes comprehensive experimental protocols that aims to
strengthen the causal relation between the reported asynchronous microarchitecture and a
reduced power consumption compared with synchronous alternatives.
The main achievement of this work is a framework that enables the architectural exploration
of circuits using the KeyRing microarchitecture