An in-band full-duplex radio receiver with a passive vector modulator downmixer for self-interference cancellation

In-band full-duplex (FD) wireless, i.e., simultaneous transmission and reception at the same frequency, introduces strong self-interference (SI) that masks the signal to be received. This paper proposes a receiver in which a copy of the transmit signal is fed through a switched-resistor vector modulator (VM)that provides simultaneous downmixing, phase shift, and amplitude scaling and subtracts it in the analog baseband for up to 27 dB SI-cancellation. Cancelling before active baseband amplification avoids self-blocking, and highly linear mixers keep SIinduced distortion low, for a receiver SI-to-noise-and-distortionratio (SINDR) of up to 71.5 dB in 16.25 MHz BW. When combined with a two-port antenna with only 20 dB isolation, the low RX distortion theoretically allows sufficient digital cancellation for over 90 dB link budget, sufficient for short-range, low-power FD links

A Passive STAR Microwave Circuit for 1-3 GHz Self-Interference Cancellation

Simultaneous transmit and receive (STAR) allows full-duplex operation of a radio, which leads to doubled capacity for a given bandwidth. A circulator with high-isolation between transmit and receive ports, and low-loss from the antenna to receive port is typically required for achieving STAR. Conventional circulators do not offer wideband performance. Although wideband circulators have been proposed using parametric, switched delay-line/capacitor, and N-path filter techniques using custom integrated circuits, these magnet-free devices have non-linearity, noise, aliasing, and switching noise injection issues. In this paper, a STAR front-end based on passive linear microwave circuit is proposed. Here, a dummy antenna located inside a miniature RF-silent absorption chamber allows circulator-free STAR using simple COTS components. The proposed approach is highly-linear, free from noise, does not require switching or parametric modulation circuits, and has virtually unlimited bandwidth only set by the performance of COTS passive microwave components. The trade-off is relatively large size of the miniature RF-shielded chamber, making this suitable for base-station side applications. Preliminary results show the measured performance of Tx/Rx isolation between 25-60 dB in the 1.0-3.0 GHz range, and 50-60 dB for the 2.4-2.7 GHz range.Comment: 4 figures, 4 page

Ka-band full duplex system with electrical balance duplexer for 5G applications using SiGe BiCMOS technology

The current dominating communication system is 4G. However, with the increase in the data rate and in the number of users in the world, the 4G communication system has started to saturate and couldn’t manage to keep up with user demands and there is less room for progress at 4G systems. In search of finding a system that covers the future interests of users, a new communication scheme is being processed as 5G. The next generation systems require wider bandwidth, high spectral efficiency, and less latency. For these goals, designs with higher frequency and full-duplex operation mode have been started to gain attention. Developments in SiGe HBT technologies -higher fT and fmax- make them suitable for these challenges. Considering these trends which lead to the future of communication systems, in this thesis the design of Ka-band (25-32GHz) SiGe full duplex system with electrical balance duplexer for 5G applications is presented. This system is created by integrating. a duplexer, an LNA, and a PA. The electrical balance duplexer is realized by a hybrid transformer and a balancing network. The impedance of the antenna is mimicked by tuning the balancing network to provide high isolation between transmitter and receiver blocks. All the ports have better than 10dB return loss. Duplexer provides measured 39dB peak isolation at 28GHz, with 3.8dB insertion loss from the transmitter to the antenna and 4.7dB insertion loss from the antenna to receiver. The LNA achieves the measured gain of 15dB, NF of 3.5dB and OP1dB of 13.5dBm at 28GHz by including an input and an output BALUN transformer. The PA provides measured gain of 17dB and OP1dB of 14dBm at 28GH

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Architectures, Antennas and Circuits for Millimeter-wave Wireless Full-Duplex Applications

Demand for wireless network capacity keeps growing exponentially every year, as a result a 1000-fold increase in data traffic is projected over the next 10 years in the context of 5G wireless networks. Solutions for delivering the 1000-fold increase in capacity fall into three main categories: deploying smaller cells, allocating more spectrum and improving spectral efficiency of wireless systems. Smaller cells at RF frequencies (1-6GHz) are unlikely to deliver the demanded capacity increase. On the other hand, millimeter-wave spectrum (frequencies over 24GHz) offers wider, multi-GHz channel bandwidths, and therefore has gained significant research interest as one of the most promising solutions to address the data traffic demands of 5G. Another disruptive technology is full-duplex which breaks a century-old assumption in wireless communication, by simultaneous transmission and reception on the same frequency channel. In doing so, full-duplex offers many benefits for wireless networks, including an immediate spectral efficiency improvement in the physical layer. Although FD promises great benefits, self-interference from the transmitter to its own receiver poses a fundamental challenge. The self-interference can be more than a billion times stronger than the desired signal and must be suppressed below the receiver noise floor. In recent years, there has been some research efforts on fully-integrated full-duplex RF transceivers, but mm-wave fully-integrated full-duplex systems, are still in their infancy. This dissertation presents novel architectures, antenna and circuit techniques to merge two exciting technologies, mm-wave and full-duplex, which can potentially offer the dual benefits of wide bandwidths and improved spectral efficiency. To this end, two different antenna interfaces, namely a wideband reconfigurable T/R antenna pair with polarization-based antenna cancellation and an mm-wave fully-integrated magnetic-free non-reciprocal circulator, are presented. The polarization-based antenna cancellation is employed in conjunction with the RF and digital cancellation to design a 60GHz full-duplex 45nm SOI CMOS transceiver with nearly 80dB self-interference suppression. The concepts and prototypes presented in this dissertation have also profound implications for emerging applications such as vehicular radars, 5G small-cell base-stations and virtual reality

Digitally-Assisted RF-Analog Self Interference Cancellation for Wideband Full-Duplex Radios

The ever-increasing demand for more data from users is pushing the development of alternative wireless technologies to improve upon network capacity. Full-Duplex radios provide an exciting opportunity to theoretically double the available spectral efficiency of wireless networks by simultaneously transmitting and receiving signals in the same frequency band. The main challenge that is presented in the implementation of a full-duplex radio is the high power transmitter leaking to the sensitive receiver chain and masking the desired receive signal to be decoded. This transmitter leakage is referred to as self interference and it is required that this self interference signal be cancelled below the receiver noise floor to achieve the full benefits of a full-duplex radio. Cancellation of the self interference signal is realized through several techniques, categorized as passive suppression, digital cancellation, and analog cancellation. These methods all have their challenges in achieving the full amount of cancellation necessary and therefore all three techniques are typically employed in the system. In this thesis, a novel digitally assisted radio frequency (RF) analog self interference canceller is proposed to suppress the self interference signal before the receiver chain for wide modulation bandwidth signals. This canceller augments minimum complexity RF-analog interference cancellation hardware that uses an RF vector multiplier in combination with a flexible digital rational function finite impulse response filter. The simple topology reduces the number of impairments added to the system through the analog components and identifies the parameters of the proposed filter in a deterministic and single iteration algorithm. The hardware proof-of-concept prototype is built using off-the-shelf RF-analog components and demonstrates excellent cancellation performance. Using four TX test signals with modulation bandwidths of 20~MHz, 40~MHz, 80~MHz, and 120~MHz, the self interference canceller achieves a minimum of 50~dB, 47~dB, 42~dB, and 40~dB of cancellation respectively. This thesis reviews the previously proposed self interference cancellation topologies, system non-idealities that provide challenges for full-duplex implementation, and the realization of the proposed RF-analog self interference canceller