The extended codes of a family of reversible MDS cyclic codes

A linear code with parameters $[n, k, n-k+1]$ is called a maximum distance separable (MDS for short) code. A linear code with parameters $[n, k, n-k]$ is said to be almost maximum distance separable (AMDS for short). A linear code is said to be near maximum distance separable (NMDS for short) if both the code and its dual are AMDS. MDS codes are very important in both theory and practice. There is a classical construction of a $[q+1, 2u-1, q-2u+3]$ MDS code for each $u$ with $1 \leq u \leq \lfloor\frac{q+1}2\rfloor$, which is a reversible and cyclic code. The objective of this paper is to study the extended codes of this family of MDS codes. Two families of MDS codes and several families of NMDS codes are obtained. The NMDS codes have applications in finite geometry, cryptography and distributed and cloud data storage systems. The weight distributions of some of the extended codes are determined

Non-Binary Coded CCSK and Frequency-Domain Equalization with Simplified LLR Generation

International audienceIn this paper, we investigate the performance of Single-Carrier (SC) transmission with Non-Binary Low- Density Parity-Check (NB-LDPC) coded Cyclic Code-Shift Keying (CCSK) signaling in a multipath environment and we show that the combination of CCSK signaling and non-binary codes results in two key advantages, namely, improved Log-Likelihood Ratio (LLR) generation via correlations and reduced implementation complexity. We demonstrate that Maximum Likelihood (ML) demodulation can be expressed by two circular convolution operations and thus it can be processed in the frequency domain. Then, we propose a joint Frequency-Domain Equalization (FDE) and LLR generation scheme that aims at reducing the complexity of the receiver. Finally, we demonstrate through Monte-Carlo simulations and histogram analysis that this proposed CCSK signaling scheme gives more robustness to SC-FDE systems than commonly employed Hadamard signaling schemes (a gap of 1.5dB in favor of CCSK signaling is observed at BER = 10−5, assuming perfect Channel State Information)

A Versatile Multi-Input Multiplier over Finite Fields

Multiplication of three elements over finite fields is used extensively in multivariate public key cryptography and solving system of linear equations over finite fields. This contribution shows the enhancements of multiplication of three elements over finite fields by using specific architecture. We firstly propose a versatile multi-input multiplier over finite fields. The parameters of this multiplier can be changed according to the requirement of the users which makes it reusable in different applications. Our evaluation of this multiplier gives optimum choices for multiplication of three elements over finite fields. Implemented results show that we takes $22.062$ ns and $16.354$ ns to execute each multiplication of three elements over $GF((2^4)^2)$ based on table look-up and polynomial basis on a FPGA respectively. Experimental results and mathematical proofs clearly demonstrate the improvement of the proposed versatile multiplier over finite fields

High Speed and Low-Complexity Hardware Architectures for Elliptic Curve-Based Crypto-Processors

The elliptic curve cryptography (ECC) has been identified as an efficient scheme for public-key cryptography. This thesis studies efficient implementation of ECC crypto-processors on hardware platforms in a bottom-up approach. We first study efficient and low-complexity architectures for finite field multiplications over Gaussian normal basis (GNB). We propose three new low-complexity digit-level architectures for finite field multiplication. Architectures are modified in order to make them more suitable for hardware implementations specially focusing on reducing the area usage. Then, for the first time, we propose a hybrid digit-level multiplier architecture which performs two multiplications together (double-multiplication) with the same number of clock cycles required as the one for one multiplication. We propose a new hardware architecture for point multiplication on newly introduced binary Edwards and generalized Hessian curves. We investigate higher level parallelization and lower level scheduling for point multiplication on these curves. Also, we propose a highly parallel architecture for point multiplication on Koblitz curves by modifying the addition formulation. Several FPGA implementations exploiting these modifications are presented in this thesis. We employed the proposed hybrid multiplier architecture to reduce the latency of point multiplication in ECC crypto-processors as well as the double-exponentiation. This scheme is the first known method to increase the speed of point multiplication whenever parallelization fails due to the data dependencies amongst lower level arithmetic computations. Our comparison results show that our proposed multiplier architectures outperform the counterparts available in the literature. Furthermore, fast computation of point multiplication on different binary elliptic curves is achieved

Borne sur le degré des polynômes presque parfaitement non-linéaires

19 pagesThe vectorial Boolean functions are employed in cryptography to build block coding algorithms. An important criterion on these functions is their resistance to the differential cryptanalysis. Nyberg defined the notion of almost perfect non-linearity (APN) to study resistance to the differential attacks. Up to now, the study of functions APN was especially devoted to power functions. Recently, Budaghyan and al. showed that certain quadratic polynomials were APN. Here, we will give a criterion so that a function is not almost perfectly non-linear. H. Janwa showed, by using Weil's bound, that certain cyclic codes could not correct two errors. A. Canteaut showed by using the same method that the functions powers were not APN for a too large value of the exponent. We use Lang and Weil's bound and a result of P. Deligne on the Weil's conjectures (or more exactly improvements given by Ghorpade and Lachaud) about surfaces on finite fields to generalize this result to all the polynomials. We show therefore that a polynomial cannot be APN if its degree is too large

Hardware Implementations for Symmetric Key Cryptosystems

The utilization of global communications network for supporting new electronic applications is growing. Many applications provided over the global communications network involve exchange of security-sensitive information between different entities. Often, communicating entities are located at different locations around the globe. This demands deployment of certain mechanisms for providing secure communications channels between these entities. For this purpose, cryptographic algorithms are used by many of today\u27s electronic applications to maintain security. Cryptographic algorithms provide set of primitives for achieving different security goals such as: confidentiality, data integrity, authenticity, and non-repudiation. In general, two main categories of cryptographic algorithms can be used to accomplish any of these security goals, namely, asymmetric key algorithms and symmetric key algorithms. The security of asymmetric key algorithms is based on the hardness of the underlying computational problems, which usually require large overhead of space and time complexities. On the other hand, the security of symmetric key algorithms is based on non-linear transformations and permutations, which provide efficient implementations compared to the asymmetric key ones. Therefore, it is common to use asymmetric key algorithms for key exchange, while symmetric key counterparts are deployed in securing the communications sessions. This thesis focuses on finding efficient hardware implementations for symmetric key cryptosystems targeting mobile communications and resource constrained applications. First, efficient lightweight hardware implementations of two members of the Welch-Gong (WG) family of stream ciphers, the WG$\left(29,11\right)$ and WG-$16$, are considered for the mobile communications domain. Optimizations in the WG$\left(29,11\right)$ stream cipher are considered when the $GF\left(2^{29}\right)$ elements are represented in either the Optimal normal basis type-II (ONB-II) or the Polynomial basis (PB). For WG-$16$, optimizations are considered only for PB representations of the $GF\left(2^{16}\right)$ elements. In this regard, optimizations for both ciphers are accomplished mainly at the arithmetic level through reducing the number of field multipliers, based on novel trace properties. In addition, other optimization techniques such as serialization and pipelining, are also considered. After this, the thesis explores efficient hardware implementations for digit-level multiplication over binary extension fields $GF\left(2^{m}\right)$. Efficient digit-level $GF\left(2^{m}\right)$ multiplications are advantageous for ultra-lightweight implementations, not only in symmetric key algorithms, but also in asymmetric key algorithms. The thesis introduces new architectures for digit-level $GF\left(2^{m}\right)$ multipliers considering the Gaussian normal basis (GNB) and PB representations of the field elements. The new digit-level $GF\left(2^{m}\right)$ single multipliers do not require loading of the two input field elements in advance to computations. This feature results in high throughput fast multiplication in resource constrained applications with limited capacity of input data-paths. The new digit-level $GF\left(2^{m}\right)$ single multipliers are considered for both the GNB and PB. In addition, for the GNB representation, new architectures for digit-level $GF\left(2^{m}\right)$ hybrid-double and hybrid-triple multipliers are introduced. The new digit-level $GF\left(2^{m}\right)$ hybrid-double and hybrid-triple GNB multipliers, respectively, accomplish the multiplication of three and four field elements using the latency required for multiplying two field elements. Furthermore, a new hardware architecture for the eight-ary exponentiation scheme is proposed by utilizing the new digit-level $GF\left(2^{m}\right)$ hybrid-triple GNB multipliers

Binary Hamming codes and Boolean designs

In this paper we consider a finite-dimensional vector space P over the Galois field GF(2), and the family Bk (respectively, B 17k) of all the k-sets of elements of P (respectively, of P 17=P 16{0}) summing up to zero. We compute the parameters of the 3-design (P,Bk) for any (necessarily even) k, and of the 2-design (P 17,B 17k) for any k. Also, we find a new proof for the weight distribution of the binary Hamming code. Moreover, we find the automorphism groups of the above designs by characterizing the permutations of P, respectively of P 17, that induce permutations of Bk, respectively of B 17k. In particular, this allows one to relax the definitions of the permutation automorphism groups of the binary Hamming code and of the extended binary Hamming code as the groups of permutations that preserve just the codewords of a given Hamming weight