155 research outputs found
Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation
In this paper, the authors propose the idea of a combined integer and
floating point multiplier(CIFM) for FPGAs. The authors propose the replacement
of existing 18x18 dedicated multipliers in FPGAs with dedicated 24x24
multipliers designed with small 4x4 bit multipliers. It is also proposed that
for every dedicated 24x24 bit multiplier block designed with 4x4 bit
multipliers, four redundant 4x4 multiplier should be provided to enforce the
feature of self repairability (to recover from the faults). In the proposed
CIFM reconfigurability at run time is also provided resulting in low power. The
major source of motivation for providing the dedicated 24x24 bit multiplier
stems from the fact that single precision floating point multiplier requires
24x24 bit integer multiplier for mantissa multiplication. A reconfigurable,
self-repairable 24x24 bit multiplier (implemented with 4x4 bit multiply
modules) will ideally suit this purpose, making FPGAs more suitable for integer
as well floating point operations. A dedicated 4x4 bit multiplier is also
proposed in this paper. Moreover, in the recent years, reversible logic has
emerged as a promising technology having its applications in low power CMOS,
quantum computing, nanotechnology, and optical computing. It is not possible to
realize quantum computing without reversible logic. Thus, this paper also paper
provides the reversible logic implementation of the proposed CIFM. The
reversible CIFM designed and proposed here will form the basis of the
completely reversible FPGAs.Comment: Published in the proceedings of the The 49th IEEE International
Midwest Symposium on Circuits and Systems (MWSCAS 2006), Puerto Rico, August
2006. Nominated for the Student Paper Award(12 papers are nominated for
Student paper Award among all submissions
Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU
In recent years, reversible logic has emerged as a promising computing
paradigm having application in low power CMOS, quantum computing,
nanotechnology, and optical computing. The classical set of gates such as AND,
OR, and EXOR are not reversible. This paper utilizes a new 4 * 4 reversible
gate called TSG gate to build the components of a primitive reversible/quantum
ALU. The most significant aspect of the TSG gate is that it can work singly as
a reversible full adder, that is reversible full adder can now be implemented
with a single gate only. A Novel reversible 4:2 compressor is also designed
from the TSG gate which is later used to design a novel 8x8 reversible Wallace
tree multiplier. It is proved that the adder, 4:2 compressor and multiplier
architectures designed using the TSG gate are better than their counterparts
available in literature, in terms of number of reversible gates and garbage
outputs. This is perhaps, the first attempt to design a reversible 4:2
compressor and a reversible Wallace tree multiplier as far as existing
literature and our knowledge is concerned. Thus, this paper provides an initial
threshold to build more complex systems which can execute complicated
operations using reversible logic.Comment: 5 Pages; Published in Proceedings of the Fifth IEEE International
Conference on Information, Communications and Signal Processing (ICICS 2005),
Bangkok, Thailand, 6-9 December 2005,pp.1425-142
Fabrication and characterization of a polymeric microcantilever with an encapsulated hotwire CVD polysilicon piezoresistor
We demonstrate a novel photoplastic nanoelectromechanical device that includes an encapsulated polysilicon piezoresistor. The temperature limitation that typically prevents deposition of polysilicon films on polymers was overcome by employing a hotwire CVD process. In this paper, we report the use of this process to fabricate and characterize a novel polymeric cantilever with an embedded piezoresistor. This device exploits the low Young's modulus of organic polymers and the high gauge factor of polysilicon. The fabricated device fits into the cantilever holder of an atomic force microscope (AFM) and can be used in conjunction with the AFM's liquid cell for detecting the adsorption of biochemicals. It enables differential measurement while preventing biochemicals from interfering with measurements using the piezoresistor. The mechanical and electromechanical characterization of the device is also reported in this paper
Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance
In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI
LDMOS with an extended-p+ region beneath the source and a stepped gate
structure in the drift region of the LDMOS. The hole current generated due to
impact ionization is now collected from an n+p+ junction instead of an n+p
junction thus delaying the parasitic BJT action. The stepped gate structure
enhances RESURF in the drift region, and minimizes the gate-drain capacitance.
Based on two-dimensional simulation results, we show that the ESG LDMOS
exhibits approximately 63% improvement in breakdown voltage, 38% improvement in
on-resistance, 11% improvement in peak transconductance, 18% improvement in
switching speed and 63% reduction in gate-drain charge density compared with
the conventional LDMOS with a field plate.Comment: Journal Pape
A Review :Implementation of Reed Solomon Error Correction & Detec-tion For Wireless Network 802.16
The reed Solomon (255,239) are error-correcting & detecting code. Reed-Solomon codes are the most frequently used digital error control. It is also called as forword error code. The main part of reed-Solomon encoder is the linear feedback shift register that is implemented using VHDL A pipelined RS decoders is proposed of reducing the hardware complexity use the pipelined GFmultiplier in the syndrome computation block, KES block, Forney block, Chien search block and error correction block for provides low com-plexity the extended inversion less Massey-Berlekamp algorithm is used. The extended inversion less Massey-Berlekamp algorithm overcomes both the error locator polynomial and the error evaluator polynomial at the same time
Low-Frequency Noise Phenomena in Switched MOSFETs
In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, the authors review the limitations of current compact noise models which do not model such single-electron effects. The authors present measurement results that illustrate typical LF noise behavior in small-area MOSFETs, and a model based on Shockley-Read-Hall statistics to explain the behavior. Finally, the authors treat practical examples that illustrate the relevance of these effects to analog circuit design. To the analog circuit designer, awareness of these single-electron noise phenomena is crucial if optimal circuits are to be designed, especially since the effects can aid in low-noise circuit design if used properly, while they may be detrimental to performance if inadvertently applie
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPROACH IN CMOS BASED CIRCUIT DESIGNING
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation
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