Modeling QCA for area minimization in logic synthesis

Abstract

Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device improvements. While significant advancements in nanotechnology devices have been achieved, much work is required to integrate these technologies into the existing design methodologies. Given that the physical design paradigm of each nanotechnology will be significantly different than that of traditional silicon circuits, the underlying cost functions used in optimization algorithms throughout the design abstraction hierarchy must be altered. Because nanotechnologies are not as well developed and understood as silicon devices, abstraction will initially result in less accurate models. However, if models are developed and augmented as nanotechnologies continue to evolve, the transition from CMOS-based design to nano-based design will be relatively seamless. This paper details the logic-level abstraction process for area minimization for one promising nanotechnology – quantum cellular automata (QCA). The model abstracts relative area costs, including interconnect area, for QCA devices, and it is integrated within existing multi-level logic synthesis techniques. Results validate the proposed approach of designing nano-based circuits with the traditional abstraction-based design methodology