Interconnect fatigue design for terrestrial photovoltaic modules

The results of comprehensive investigation of interconnect fatigue that has led to the definition of useful reliability-design and life-prediction algorithms are presented. Experimental data indicate that the classical strain-cycle (fatigue) curve for the interconnect material is a good model of mean interconnect fatigue performance, but it fails to account for the broad statistical scatter, which is critical to reliability prediction. To fill this shortcoming the classical fatigue curve is combined with experimental cumulative interconnect failure rate data to yield statistical fatigue curves (having failure probability as a parameter) which enable (1) the prediction of cumulative interconnect failures during the design life of an array field, and (2) the unambiguous--ie., quantitative--interpretation of data from field-service qualification (accelerated thermal cycling) tests. Optimal interconnect cost-reliability design algorithms are derived based on minimizing the cost of energy over the design life of the array field

Pressurized bellows flat contact heat exchanger interface

Disclosed is an interdigitated plate-type heat exchanger interface. The interface includes a modular interconnect to thermally connect a pair or pairs of plate-type heat exchangers to a second single or multiple plate-type heat exchanger. The modular interconnect comprises a series of parallel, plate-type heat exchangers arranged in pairs to form a slot therebetween. The plate-type heat exchangers of the second heat exchanger insert into the slots of the modular interconnect. Bellows are provided between the pairs of fins of the modular interconnect so that when the bellows are pressurized, they drive the plate-type heat exchangers of the modular interconnect toward one another, thus closing upon the second heat exchanger plates. Each end of the bellows has a part thereof a thin, membrane diaphragm which readily conforms to the contours of the heat exchanger plates of the modular interconnect when the bellows is pressurized. This ensures an even distribution of pressure on the heat exchangers of the modular interconnect thus creating substantially planar contact between the two heat exchangers. The effect of the interface of the present invention is to provide a dry connection between two heat exchangers whereby the rate of heat transfer can be varied by varying the pressure within the bellows

Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design

Optimal Positions of Twists in Global On-Chip Differential Interconnects

Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-mum CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstal

Leakage-Aware Interconnect for On-Chip Network

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.Comment: Submitted on behalf of EDAA (http://www.edaa.com/

Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique

Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination. RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.Comment: 12 Figures, appears in Electrical and Electronics Engineering: An International Journal, November 201

Layout-driven allocation for high level synthesis

We propose a hypergraph model and a new algorithm for hardware allocation. The use of a hypergraph model facilitates the identification of sharable resources and the calculation of interconnect costs. Using the hyper graph model, the algorithm performs interconnect optimization by taking into account interdependent relationships between three allocation subtasks: register, operation, and interconnect allocations simultaneously. Previous algorithms considered these three tasks serially. Another novel contribution of our algorithm is the exploration of design space by trading off storage units and interconnects. We also demonstrate that traditional cost functions using the number of registers and the number of mux-inputs can not guarantee the minimal area. To rectify the problem, we introduce a new layout area cost function and compare it to the traditional cost functions. Our experiments show that our algorithm is superior to previously published algorithms under traditional cost functions

Interconnect research influenced

This article shows that Rent's rule can be viewed as a fundamental law of nature with respect to electronic circuits. As there are many interpretations of the rule, this article will shed some light on the core of Rent's rule and the research that has been built on it

Multiport VNA Measurements

This article presents some of the most recent multiport VNA measurement methodologies used to characterize these highspeed digital networks for signal integrity. There will be a discussion of the trends and measurement challenges of high-speed digital systems, followed by a presentation of the multiport VNA measurement system details, calibration, and measurement techniques, as well as some examples of interconnect device measurements. The intent here is to present some general concepts and trends for multiport VNA measurements as applied to computer system board-level interconnect structures, and not to promote any particular brand or produc