Digital computer aided circuit analysis and desig

Koonce, H. T.

Yang, T.

English

NASA Technical Reports Server

Semi-Annual Report on 
Computer-Aided Circuit Analysis 
Submitted to 
NATIONAL AERONAUTICS AND SPACE ADMINISTRATION 
Office of Grants and Research Contracts 
Washington D. C. 20546 
This work was done under the NASA grant 
NGR-39-023-004, during the period May 15 
to  November 14, 1966, at the Electrical 
Engineering Department, Villanova University 
Villanova, Pennsylvania. 
PRINCIPAL INVESTIGATOR 
Professor of Eleckcal Engineering 
-&&- 
Director of Rese 4 6  and Development ? 
RESEARCH AND DEVELOPMENT DIVISION 
VILLANOVA UNIVERSITY 
- .  
VILLANOVA, PENNSYLVANIA 
https://ntrs.nasa.gov/search.jsp?R=19670004879 2020-03-16T17:09:03+00:00Z
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Semi-Annual Report of the Research on 
Digital Computer-Aided Circuit Analysis 
under the NASA Grant NGR-39-023-004 
covering period from May 15 to November 14, 1966 
I. Bibliography Updating 
A continual effort is maintained to update the "Bibliography on Computer-Aided 
Circuit Analysis and Design"* which was prepared in 1965 and included with revisions 
in the 1966 Annual Report** of this research. New entries of the titles since then are 
listed as follows: 
R. C. Amara, "Computer Design and Control of Probabilistic Communication 
Networks", IRE Trans. on Communication Systems, vol. CS-11, pp. 30-35; 
March, 1963. 
J. B. Atkins, "Worst-Case Circuit Design', IEEE Spectrum, vol. 2, pp. 
152-161; March, 1965 
Autonetics Di-Jision, North American Aviation Inc. "Reliability Analysis of 
Electronic Circuits'', Autonetics, Anaheim, Calif. , 1964, 
W. V. Bell, J. E. Kernan and P. H. Holub, "Computer-Aided Analysis of a 
Silicon Monolithic Integrated Current Switch Gate", Proceedings of 9th 
Midwest Symposium on Circuit Theory, May, 1966, 
A. D. Bhalla, "Computer Calculations of Transistor Amplifier Performance 
from Measured Y-Parameters", IEEE Trans, on Broadcast and TV Receivers, 
pp. 33-43, December, 1965. 
R. T. Byerly, R. W. Long and C. W. Wing, "Logic for  Applying Topo- 
logical Methods to Electric Networks", Comm. and Electronics, no. 39 
(AIEE Trans. vol. 77 pt. l ) ,  pp. 657-667; November, 1958. 
N. K. M. Chitre and M. V. O'Donovan, :Computer-Aided Design of Waveguide 
Filters", RCA Engineer, vol. 12, no. 1, pp. 74-77; June-July, 1966. 
C. A. Combs, Jr., "Stanpak, GET Program Abstract", General Electric Co., 
Phoenix, Ariz. ; November, 1965. 
W. E. Craig and H. W. Mathers, "Digital Computer Techniques for Determining 
Circuit Behavior in a Pulsed Nuclear Environment", IEEE Trans. on Nuclear 
Science, vol. NS-10, pp. 168-175; November, 1963. 
* NASA-CR-70211 (N66-16980) 
** NASA-CR-76373 (N66-31224) 
- 1 -  
.. 
M .  L. Dertouzos and C. Therrien, "An Iterative Approach for Network 
Analysis", Status Report ESL-SR-225, MIT Project DSR 9948; Electronic 
Systems Laboratory, Mass. Inst. Tech., December, 1964. 
and P. J. Santos, Jr.,  "CADD: On-Line Systhesis of Logic 
Circuits", Report ESL-R-253, MIT Project DSR 9948; Electronic Systems 
Laboratory, Mass,  Inst, Tech. : December: 1965, 
and J. F. Reintjes, IfComputer-Aided Electronic Circuit 
Design", Project MAC Progress Report 11, pp. 81-87; Mass. Inst, Tech. , 
July, 1965. AD 629 494, 
D. L. Dietmeyer and P. R. Schneider, "A Computer Oriented Factoring 
Algorithm for  NOR Logic Design", IEEE Trans, on Electronic Computers, 
vol, EC-14 pp, 868-874, December, 1965. 
H. Falk, "Computer Programs for Circuit Design'' , Electro-Technology, 
vol. 75, no. 6, pp. 54-57; June, 1966. ' 
E. W. Hobbs, "Topological Network Analysis as a Computer Program", 
IRE Trans. on Circuit Theory, vol. CT-6, pp. 135-136; March, 1959. 
J. Katzenelson, "AEDNET: A Simulator for Nonlinear Networks", Proc. 
IEEE vol. 54, November, 1966. 
W, Mayeda aiid S. Seshu, "Generation of Trees  Without DuplicationTf, 
IEEE Trans. on Circuit Theory, vol. CT-12, pp. 181-185; June, 1965. 
Norden Division, United Aircraft Corp. , "Development of Techniques for 
Automatic Manufacturing of Integral Circuits" in two volumes, Tech. Rept. 
AFML-TR-65-386; Norden, Norwalk, Conn. ; November, 1965. 
D. E. Scott and D. Waterman, 'IComputer Design of Chebyshev Filters", 
Electro-Technology, vol. 78 no, 5, pp, 111-112, November, 1966. 
S. R. Sedore, "Evaluation and Compensation of Digital Switching Circuits 
in Transients Radiation Environments", IEEE Trans. on Nuclear Science, 
vol, NS-10, pp. 159-167; November, 1963. 
C .  L. Semmelman, "Analysis and Synthesis of Linear Networks", Seminar on 
U s e  of Computers in Network and System Design, National Electronics 
Conference, October 4, 1966, Chicago, 111. 
H. Wall  and H. Falk, "Circuit Analysis by Computert1. Electro-Technology, 
vol, 78 no. 5, pp. 50-56, November, 1966. 
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11. Evaluation Study of Available Programs -- STANPAK 
The General Electric Company at Phoenix, Arizona, has developed a reliability 
prediction and tolerance analysis and adjustment program called STANPAK, 
- Statistical - Tolerance _Analysis _Package. Given a set  of functions and parameters data, 
the program may be used to compute the nominal output values and the mean, the 
variance and tolerance limit for  the dependent variable. It can determine the principal 
sources of variation, relax o r  tighten component tolerances until given specifications 
a r e  met at a reliability level. In addition, a M0nt.e Carlo analysis can be performed. 
The component values are selected randomly from their distribution and the dependent 
variables a re  computed. 
times and the distribution of the result is tabulated. 
This procedure is repeated for a prescribed number of 
Because the time sharing computer facilities have been established between 
Villanova University and the Space Technology Center of General Electric Company 
at  King of Prussia, Pa. for some time, a reduced version of STANPAK was put into 
test  via the Desk Side Computer at the Villanova input terminal this summer. 
Operational difficulties were first experienced and then resolved. In the original 
writeup of STANPAK program, it has  the capability to handle thirty parameters and 
seven different functions, a function being defined as an algebraic expression in which 
every variable except the dependent variable is either an input variable o r  a previously 
computed variable. In essence, each function is an equation in one unknown. 
In the adaption of the program to our local operation, the control and print- 
out procedures have been modified. A paper entitled "A Survey of Application of 
Digital Computers to General Circuit Analysis", which examines STANPAK in the light 
of other available programs of circuit analysis such as ASAP, CIRCUS, ECAP, and 
NET-1, was  prepared and issued as  a separate technical memorandum to NASA 
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r .  
111. 
in October, 1966. The detailed description of the changes made on the program, 
special notes or  hints and kinks for new users, and illustrative working examples 
will be included in a later report, 
Signal Flow Graphs -- Signal flow graphs (SFG) were introduced by Masonl, and 
further developed by Lorens2, Happ3 and others. 
The problem under study is the solution of network responses in the time 
domain using the theory of the SFG with the aid of a small digital computer (IBM-1620). 
Primitive Signal Flow Graph -- Mason1 developed the procedure for determining the 
primitive signal flow graph (PSFG), which was later modified by Happ4 for  digital 
computer programming, The PSFG i s  developed by considering all elements of the 
network under study to be composed of voltage generators and current generators, 
For example, a transistor circuit, base resistance, would be classified a s  a current 
generator if the base resistance current IB develops the dependent current source 
BIB. The PSFG appears better suited fo r  development by digital computer programming, 
than the usual procedure of writing appropriate circuit equations and developing the 
SFG from these equations, 
The procedure for determining a PSFG is a s  follows: 1) designate all elements 
of the network as either current generators or  voltage generators; 2 )  choose a tree 
of the network topology containing all of the voltage generators, but none of the current 
generators; 3 )  determine each link-branch voltage in terms of tree-branch voltages; 
4) determine each tree-branch current in terms of link-branch currents; 5 )  for each 
circuit element use two nodes, a voltage node and a current node; 6 )  the voltage and 
current transmittances a re  determined from steps 3 and 4; 7 ) the link-branch 
elements are connected between respective V and I nodes by admittance transmittances 
and the tree-branch elements by impedance transmittances, An example i s  given to 
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illustrate the development of the PSFG, with some comments to indicate the algorithm 
used to aid in writing a digital computer program. 
Fig. 1. Common emitter transistor amplifier circuit 
The network topology is shown in fig. 2a for  the equivalent circuit of fig. 1, 
and the tree ( solid lines) and cotree (dotted lines) of fig. 2b, indicate the elements 
designated a s  voltage and current generators respectively. Each element of the network 
is  
I 2 €4 3 
Fig. 2 Topological diagrams of Fig. 1 
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numbered, and the arrow indicates the direction of current with the voltage being 
positive on the node of the arrow head, Note that edge E2, the base resistance, is 
a link branch a s  mentioned above, Two approaches have been considered for writing 
a program to determine a tree. One is to select at random a combination cf edges 
and check that it is a tree, The other approach is to search through the edges for 
all vertices, checking that no closed loops a re  formed during the search. In general 
many t rees  can be formed from a network, but restricting some of the branches to 
link o r  t ree  branches will reduce the number of possible tree selections. 
To construct the PSFG, voltage nodes and current nodes for each circuit 
element are drawn as in fig. 3. 
/ 
V 0 
1 0 
2 3 4 5 
0 0 0 0 
0 0 0 0 
Fig. 3 Voltage and current nodes for the PSFG. 
Then Kirchoff's constraints for the link-branch voltages in terms of tree- 
branch voltages a re  determined by loop equations 
(1) v2 = -v1 - v 3  
( 2 )  v4 = v 5  - v 3  
The equations for the tree-branch currents in terms of link-branch currents 
are 
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L. 
2 ( 3 )  11 = I 
( 4 )  
( 5 )  14 = BIZ 
13 = I2 + I4 
( 6 )  = -I4 
A program has been written to develop these equations, based on the concept 
of the incidence matrix of a circuit. 
Actually since the two sets of equations a re  related, it  i s  only necessary to 
determine one set  of equations, Fig, 4 shows the nodes with the constraint trans- 
in ittance s added. 
Fig. 4 Flow graph with Kirchoff's constraints 
Next the passive element transmittances a re  added to the diagram as  shown in fig. 5, 
The tree-branches are impedance transmittances and the link branches are admittance 
transmittances with the former oriented from I-nodes to V-nodes and the latter from 
V-nodes to I-nodes, 
and I4 a re  sources, 
Note that nodes V4 and TI are  the terminating nodes since VI 
The reduction of the PSFG will be done according to the node absorption 
procedure. A program developed by Abrahams5 which reduces nodes consisting of 
transmittances that a re  real  numbers has been modified to process transmittances 
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that are a function of complex frequency using the non-numerical algebra. 
The inverse Laplace transform to obtain the time domain response of the 
T 
J 
I 
r. 
circuit will be done by a program based 
1 2 3 
I (  z3- Y yz" h t 3  
c ,-. J n c 
on Liou's6 method. 
4- 5- 
L. 
1: c 1 c> rc  n cc s 
( 1 ) S. J. Mason and H. J. Zimmerman, "Electronic Circuits, Signals and 
S.vstcnis'l, John Wiley 1960. 
( 2 )  C.  S. Lorens, "Flowgraphs", McGraw-Hill 1964. 
( 2 )  W. W. Happ, "Dynamic Characteristics of Four-Terminal Networks", 
Institute of Radio Engineers Convention Record, Pt. 2, 1964. 
( 4 )  W. W. Happ, "Flowgraphs as a Teaching Aid", IEEE Transactions on 
Education, May 1966. 
( 5 )  J. R. Abrahams, "Amplifier Design with a Digital Computer'', Electronic 
Engr. Vol. 37, pp. 740-745, November 1965. 
( 6 )  M. L. Liou, "A Novel Method of Evaluating Transient Response", Proc. of 
IEEE, January 1966. 
IV. Future Plans 
1. Continue the signal flow-graph approach of circuit analysis within the constraints 
of a moderate size computer. There are  three essential steps to the complete 
solution: 
( a )  development of signal flow-graph from the 
network topology. 
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, 
( b )  reduction of signal flow-graph to obtain the 
transfer function, and 
time-domain solution of the desired output quantity. ( c) 
The second and third steps have been considered and they present no special 
difficulties. The first  step seems to be the most challenging of all three in the 
implementation by computer programs. Inherently, the problem of realizing a 
proper signal flow-graph from circuit diagram possesses the same elusive features 
as other pattern recognition problems. It is expected that research effort will be 
directed toward gaining more insight into this intuitively simple problem and uncover- 
ing a method of its solution 
2, Non-numerical manipulation by digital computers is an area of growing 
interest to the computer users. The August, 1966 issue of the Communication of 
the Association for Computing Machinery was devoted entirely to the papers on 
Symbolic and Algebraic Manipulations, A s  far as the circuit analysis and design is 
concerned, the symbolic manipulation would be useful in reducing the accumulated 
e r r o r s  in iterative computation and optimizing the dependent variable with respect 
to a given set  of parameters. In the method of signal flow graph analysis the non- 
numerican formula, once implemented in the program, will enable the analysis of a 
circuit to be carried out in the most generalized manner, Initial attempt on poly- 
nomial manipulations, root finding and other simple mathematical operations will 
gradually lead us to more interesting explorations. 
3. Since the transient response of a network is the ultimate objective of circuit 
analysis, development and examination of new techniques in transient solution i s  always 
of direct consequence to circuit designers. The novel method proposed by Liou in 
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, 
+ 
the Proceedings of the IEEE, January, 1966, deserves our serious attention and 
experimentation. Application of Liou's method to general circuit problems has been 
started and will be continued through the months to come. Eventually it will be 
critically compared With other classical methods of solution of ordinary dif€erer,tial 
equations as to its mertis o r  demertis. 
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Computer-aided Circuit Analysis Semiannual Report, May 15 - Nov. 14, 1966

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