de Cuveland, J.

Hutter, D.

Lindenstruth, V.

GSI Repository

CBM FLES input interface developments∗D. Hutter1, J. de Cuveland1, and V. Lindenstruth11FIAS Frankfurt Institute for Advanced Studies, Goethe-Universita¨t Frankfurt am Main, GermanyThe First-level Event Selector (FLES) is the centralevent selection system in the CBM experiment. Its task is toselect data for storage based on online analyses including acomplete event reconstruction. To do so, the FLES times-lice building has to combine data from all input links totime intervals and distribute them to the compute nodes. Toallow for efficient timeslice building, detector data streamsare partitioned into microslices prior to combining them.Microslices are specialized containers covering a constanttimeframe of real time, which is the same for all subsys-tems. This allows data agnostic, subsystem independenttimeslice building. This partitioning will be done by theData Processing Boards (DPB) as they are the last stage ofthe read-out tree which has to contain subsystem specificcomponents.The FLES input interface is realized by a custom FPGAPCIe card, the FLES Interface Board (FLIB). Its purposeis to provides the optical interface to the DPBs as well asthe interface to the FLES input nodes. The current devel-opment is based on the commercial HTG-K7-PCIE boardform Hitech Global. It features a Xilinx Kintex-7 FPGA,a 8x PCIe 2.0 interface, up to eight 10 GBit/s links andoptionally 8 GB of DDR3 memory.The FPGA design includes the protocol for receivingmicroslices, a pre-processing engine preparing microslicesfor timeslice building and a custom full off-load DMA en-gine. Once configured the DMA engine is capable of con-stantly transferring microslices and meta data to the PCsmemory without involving the host CPU. The only taskthe CPU needs to perform is to acknowledge processeddata segments occasionally to allow reusing buffer space.A measurement of the DMA performance for one to four10 Gbit/s microslice streams is given in Fig. 1. For upto three steams, data is transmitted at full input speed.For four streams, the input data rate exceeds the avail-able PCIe bandwidth. The achieved maximum data rateis 3345 MB/s, which matches the absolute maximum PCIedata rate for the given configuration.For demonstration and testing the input interface conceptin real live applications, the FLIB and flesnet software havebeen used for read-out in the CERN-PS 2014 testbeam atT9 beamline. In contrast to the final system, current se-tups lack the DPB layer and do not support the creation ofmicroslices. A specialized FLIB prototype firmware there-fore includes a mockup of the DPB design and is capa-ble of directly receiving CBMNet messages as deliveredby the CBM front-end electronics. Simplified microslices∗Work supported by BMBF (05P12RFFCP) and HIC for FAIR 500 1000 1500 2000 2500 3000 3500 40001 k 10 k 100 k 1 MBandwidth [MB/s]max. microslice size [Byte]1 link raw1 link total2 links raw2 links total3 links raw3 links total4 links raw4 links totalFigure 1: FLIB read-out bandwidth 0 100 200 300 400 500 600 700 800 90011-2100:0011-2112:0011-2200:0011-2212:0011-2300:0011-2312:0011-2400:0011-2412:0011-2500:0011-2512:0011-2600:00Size in GBDateRecorded Data over Timetotal data recordedrun sizeFigure 2: Recorded testbeam data over timeare generated inside the FLIB and subsequently handled inthe same way as foreseen for the final setup. Thus the setupis capable of delivering fully build timeslices to any givenconsumer. In case of the testbeam, timeslices were writtento disk and simultaneously published via a ZMQ socket toCBMroot clients for front-end calibration and online moni-toring. In addition the firmware and software includes sup-port for front-end configuration and synchronization overCBMnet which is accessible via a ZMQ interface or fromwithin CBMroot.During the testbeam a single FLIB in conjunction withthe flesnet software was successfully used to read-out up tosix detector setups in different configurations. Three dif-ferent flavors of data sources have been employed, Syscore2, Syscore 3 and TRB boards. Figure 2 shows an overviewover five days of data taking. In total 888 GB of data in 84runs was written to disk without any major read-out relatedproblems. Online performed data consistency checks andfirst offline analysis did not reveal any issues with the data.To support future setups including DPBs the FLES in-terface module is currently under development. It will pro-vide a 10 GBit/s link transferring microslices to the FLIBenabling full featured microslice creation on the DPBs.MU-NQM-CBM-12 GSI SCIENTIFIC REPORT 201448 DOI:10.15120/GR-2015-1-MU-NQM-CBM-12

CBM FLES input interface developments

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CBM FLES input interface developments

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