Busson, P

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Overview of the new CMS electromagnetic calorimeter electronics.Ph. BussonLaboratoire Leprince-Ringuet, CNRS/IN2P3, Route de Saclay, F-91128 Palaiseau, Cedex, Francebusson@poly.in2p3.frAbstractSince the publication of the CMS ECAL Technical DesignReport end of 1997 the ECAL electronics has experienced amajor revision in 2002. Extensive use of radiation hardtechnology digital electronics in the front-end allowssimplifying the Off-Detector electronics.The new ECAL electronics system is described withemphasis on the Off-Detector sub-system.I. THE ECAL ELECTRONICS IN THE  TECHNICALDESIGN REPORTIn the CMS electromagnetic calorimeter Technical DesignReport the principle of maximal flexibility for the ECALelectronics system was adopted.The CMS electromagnetic calorimeter is a very highresolution calorimeter made of 80000 lead tungstate crystals.Each crystal signal generated by an APD is amplified,sampled and digitized with an ADC working at 40 MHzfrequency. The adopted solution for the TDR was to processdigitally all signals in the Off-Detector electronics sub-systemlocated outside the CMS cavern. This principle translated in asystem sub-divided into two distinct sub-systems namely:- a Very Front-End electronics, mainly analogue, with amulti gain amplifier and an ADC designed in radiation hardtechnology connected to each crystal equipped with an APD.The digital signal was converted to serial optical signal.- an Off-Detector electronics mainly developed in digitalelectronics making use of FPGA circuits located outside theCMS cavern.The two sub-systems were connected with 80000 serialoptical links working at 0.800 Gbits/s.The Off-Detector electronics was designed to receive thishuge amount of digital data and to subsequently store andprocess them during the L1 latency of 3 microseconds. Thedesigned sub-system had 60 crates with more than 1000boards.I. THE NEW ARCHITECTUREIn 2002 the ECAL electronics system was reviewed and anew architecture making use of new radiation hard electronicsinside the detector volume was adopted. In this schema,digitized data are locally stored in memories and processedduring the L1 latency. Only data corresponding to the L1accepted events are readout by the Off-Detector systemallowing for a substantial reduction in complexity of this sub-system. The interface with the Trigger system is also greatlysimplified in this new architecture which is less than 220boards in total.A block diagram of this new architecture is shown inFigure 1.  The Front-End electronics is presented in chapterIII while the components of the Off-Detector electronics aredescribed in chapter IV.Figure 1: Block diagram of the new ECAL ElectronicsI. THE FRONT-END ELECTRONICSThe Front-End electronics performs the followingfunctions:a) reception of the digital signals from the Very-Frontelectronics,  ie 16 bits delivered at 40 MHz. These 16bits contain 12 bits from the sampling ADC and 2 bitsencoding the gain used by the amplifier stagea) storage the data during the L1 latencya) generation of the Trigger Primitivea) formatting and transmission of the data to the DCCfor each L1 accept signala) transmission of the Trigger Primitives to the TCCwith a 40 MHz clockThe Front-End electronics will mainly sit on Front-Endboards serving 25 crystals each. A possible implementation ofthe Front-End board is shown in Figure 2 in the case of thebarrel.The 25 digital signals generated by the Very-Front-Endelectronics are distributed to the FE board via connectorslabelled VFE.x (with x from 1 to 5). Each signal is transmittedfrom the VFE at 40 MHz. These input signals are distributedto 5 FENIX circuits (Strip Fenix in the figure). Two additionalFENIX chips, TCP Fenix and DAQ Fenix are fed by theoutput signals (16-bit each) from the 5 Strip FENIX circuits.Figure 1: The Front-End Board (barrel implementation)The DAQ Fenix sends the crystals data to the DCC afterreception of a L1 signal accept. A Giga Optical Link circuit(GOL) is responsible for this transmission The TCP Fenixsends the Trigger Primitives to the TCC boards via a secondGOL chip.The FENIX chip[1], sitting on the Front-End board has 5input 16-bit buses working at 40 MHz and two outputs 16-bitbuses.The FENIX chip has four operation modes:a) STRIP operation mode whose purpose is to create thestrips (5 crystals aligned along the phi direction)signals in the barrel) or the pseudo-strips (groups of 5crystals with any shape) signals in the endcap.a) TCP operation mode whose purpose is to compute theTrigger Primitives for a trigger tower (5 strips) in thebarrel casea) DAQ operation mode whose purpose is the storage ofthe crystals data from a trigger tower in the barrel or asupercrystal (5 pseudo-strips) in the endcapa) MEM operation mode whose purpose is to performthe readout of the laser monitoring dataThe trigger path of the FENIX chip when it is operating inSTRIP mode is shown in Figure 3. Figure 4 shows the triggerpath in the FENIX running under the TCP operation mode.Under both operation mode the FENIX performs thecomputations used in the Trigger Primitives Generation inpipeline mode. The following computational stages areperformed in the FENIX STRIP mode:a) LIN: transforms the non-linear input scale generatedby the VFE into a linear transverse energy scaletaking into account the calibration factor for eachchannela) ETSTRIP: adds the five inputsa) AMPLITUDE FILTER and PEAK FINDER:perform together the Bunch Crossing IDentification .The AMPLITUDE FILTER is a 5-tap FIR filter andthe PEAK FINDER is a 3-point peak detector.a) FORMAT:  conditions the output of the amplitudefilter by the detected peak found in the PEAKFINDERFigure 1: The FENIX chip in STRIP operation mode (only thetrigger path is shown)In the case of the TCP operation mode, only used in thebarrel case, the FENIX circuit has the following  pipelinestages:a) ETTOT: computes the total transverse energy of thetrigger towera) MAXof2 and FGVB(EB): perform together theextraction of the Fine Grain Veto Bita) FORMAT: encodes the total transverse energy andthe fine grain veto bit in a single wordThe FENIX chip will be founded in 0.25 mm CMOStechnology in order to resist to the high level of radiation inwhich the Front-End board is working.The VHDL description of the FENIX chip has been alreadydownloaded to a field programmable gate array circuit, theXC2V1000 from Xilinx company.Preliminary simulations, performed in the FPGA version ofthe FENIX chip, show that the computations of the TriggerPrimitives, as done in the pipeline chain formed by theFENIX STRIP and FENIX TCP take 225 ns, i.e 9 cycles ofthe LHC clock.In order to fulfil the specifications the ASIC version of theFENIX chip this latency should be decreased to 8 clockcycles.Figure 2: The FENIX chip in TCP operation mode (only the triggerpath is shown)II. THE OFF-DETECTOR ELECTRONICSThe Off-Detector electronics [2] is composed of severaltypes of boards:a) Clock and Control Systemb) Data Concentrator Cardsc) Trigger Concentrator Cardsd)  Selective Readout Processorwhich are described in the following chapters.A. The Clock and Control SystemThe CCS is the central body of the 0ff-Detectorelectronics. It receives the control signals as well as the LHCclock from the Trigger and Time Control (TTC) system andthe Trigger Throttling System (TTS) and sends it back to theTrigger Concentrator Cards and to the Data ConcentratorCards.It also performs the setting-up of the Front-End via opticalcontrol loops.The CCS functions are:a) optical to electrical conversion of the TTC fibrereceived from the TTC optical fan-outb) decoding of the TTC signal for extraction of the LHCclock and the command signalsc) reception  of the TTS signals transmitted by the DCCand TCC. After collecting these signals the CCS sends it tothe TTSd) setting-up of the Front-End boards via a network ofoptical fibres.B. The Data Concentrator CardThe DCC is a common collection point for crystal datatransmitted from up to 68 Front-End boards and for triggerdata transmitted from up to 5 TCC modules after level 1accept trigger signal.The DCC is also responsible for reading data from twomonitoring channels.The DCC functions are:a) optical to electrical conversion and deserialisation ofthe serial input streamsb) verification of the integrity of the input eventfragmentsc) reduction of the data volume using a combination ofcrystal zero suppression and tower selective readoutd) formatting of DCC eventse) transmission of DCC events to the global DAQthrough the standard DAQ linkf) transmission of the monitoring events and spyingevents to the local DAQThe DCC accepts several types of events: physics eventsand monitoring events (laser, monitoring test pulse,leakage current and temperature measurements).The DCC is designed to accept a total of 38.1 kBytes forinput crystal event size and 156 bytes (barrel) and 300bytes (endcap) for input TCC event.The average output data rate to the global DAQ is 200Mbytes/s with a maximum peak output data of 528Mbytes/s. The DCC is designed to store a maximum of 32events.The DCC verifies the integrity of the input data byperforming various checks. It implements mechanisms forprotecting memories from overflows and signalsconditions of overflows to the TTS system via the CCS.The data reduction can be set up, following two readoutmodes: Forced Readout or Selective Readout. In ForcedReadout mode the DCC selects the readout region ofECAL using a programmable map defined by conditionsset without regard to the current event. In the contrary, theSelective Readout mode the readout is determineddynamically by the Selective Readout Processor. Threecases are considered: read all crystals, read crystals abovezero suppression threshold, do not read crystal data.The zero suppression is based on the estimation of thecrystal energy performed by a 10-tap FIR filter. The filtercoefficients are programmable individually per crystal.The DCC is implemented in a VME9U board. The DCCdiagram is shown in Figure.Figure 3: The DCC block diagramThe 68 optical links from the Front-End boards and the 2additional optical links from the monitoring are shown in thisfigure.After optical to electrical conversion and deserialisationinto 16-bit words input data  enter the Receiver Blocks (onefor two channels) The Receiver Block performs link and dataintegrity checks, data suppression and event storage withinput iFIFOs.The Event Builder Blocks are responsible to move eventfragments from the iFIFOs into the output oFIFOs. Data in theoFIFOs is transmitted to DAQ through the S-Link 64 at amaximum rate of 528 Mbytes/s.C. The Trigger Concentrator Card andSynchronization and Link BoardThe TCC collects data transmitted from 68 Front-Endboards in the barrel and up to 48 Front-End boards in theendcap. This corresponds to 68 trigger towers signals in thebarrel and up to 48 pseudo-strips signals in the endcap. TheTCC is also responsible to generate the classification oftrigger towers for the Selective Readout Processor.The TCC functions are:a) optical to electrical conversion and deserialisation ofthe input data streamsb) geometrical mapping between the pseudo-strips andthe trigger towers in the endcapc) finalization of the trigger primitives generation in theendcapd) encoding of the trigger primitives using a non-linearscale for the total transverse energy deposited in thetrigger towere) time alignment and transmission of the encodedtrigger primitives to the Regional Trigger systemf) classification of each trigger tower into high, mediumor low interest for the Selective Readoutg) storage of the encoded trigger primitives during theL1 latencyh) transmission of the TCC events to the DCCIn the endcap the TCC receives signals from the pseudo-strips. Depending on the endcap region covered by theTCC under consideration the trigger towers signals arebuild using different groups of pseudo-strips signals.In order to avoid the design of several types of TCC asingle routing has been designed allowing the distributionof the relevant pseudo-strips signals to four processingunits. These processing units will be programmed in sucha way that they will combine the pseudo-strips signals toform the trigger towers signals.The TCC is implemented on a VME9U board. The blockdiagram for the endcap design is shown in Figure 6.After optical to electrical conversion and deserialisationinto 16-bit words the 48 (68 in the barrel case) input dataenter 4 Processing Units (6 in the barrel case). These unitsare responsible for the finalisation of the trigger primitivesin the endcap. For both barrel and endcap versions theTCC encodes the total transverse energy in a non-linearscale and classifies the trigger towers in three categoriesdepending on the total  transverse energy. The ProcessingUnits stores the encoded trigger primitive during the L1latency for subsequent reading by the DCC.Figure 4: The TCC block diagram (endcap)The encoded trigger primitives (8 bits for the non-linearrepresentation of the total transverse energy plus 1 bit for thefine grain veto) are time aligned and sent to the RegionalTrigger by a dedicated daughter board, the Synchronisationand Link Board (SLB in Figure 6).  Each SLB handles amaximum of 8 encoded trigger primitives. It formats the 8corresponding words in order to be sent via a single Vitesse7216 chip with a 2 Gbits/s capacity connected to the RegionalTrigger system by a copper link.As one can anticipate, the high number of input and outputsignals will highly  influence the implementation of the TCCeither for the endcap or barrel case.III. SUMMARYThe new ECAL electronics architecture has beenpresented. This architecture has exactly the same functionalityas described in the Technical Design Report of the ECAL butwith a substantial reduction (40%) in the estimated cost.The newly introduced Front-End electronics essentiallyrely on the design of a new radiation  hard circuit, the FENIXchip. The design of this chip in 0.25 mm CMOS technology isalready started. Submission of this design is expected to takeplace end of 2002.The flexibility principle, which was adopted in theTechnical Design Report, has been abandoned. This allowsthe new architecture to use a reduced number of optical datalinks for data exchange between the on and off-detectorelectronics.This also permits to design a more compact, more simpleand  less expensive Off-Detector electronics. The design ofthe Off-Detector electronics has recently started andproduction of the corresponding electronics modules isforeseen to start beginning of year 2004.IV. REFERENCES[1]http://mhansen.home.cern.ch/mhansen/Cms/Cms_ecal/Documentation/Fenix/Fenix.html[2]http://cmsdoc.cern.ch/~jlfaure/OD_Web_Folder/Page_web.html

Overview of the new CMS electromagnetic calorimeter electronics

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