Bulfone, D

Gamba, C

Lonza, M

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DIGITAL PROCESSING ELECTRONICS FOR THE ELETTRATRANSVERSE MULTI-BUNCH FEEDBACK SYSTEMM. Lonza, D. Bulfone, C. Gamba,Sincrotrone Trieste, S.S. 14 - Km 163.5, 34012 Basovizza, Trieste, ItalyAbstractCoupled-bunch instabilities excited by RF cavity highorder modes or resistive wall impedance can seriouslylimit the performance of third generation synchrotronlight sources like ELETTRA. These instabilities can becured by the use of active feedback systems. In the digitalbunch-by-bunch approach adopted at ELETTRA, theposition of the 432 bunches is sampled and correctedemploying 500 Msample/s A/D and D/A converters. Thecorrection values are computed by a multi-processorarchitecture made of state-of-the-art DSPs (Digital SignalProcessors). A modular design allows to use commercial-off-the-shelf (COTS) components for the most criticalparts of the system.1 SYSTEM OVERVIEWThe basic principle of a bunch-by-bunch feedback isthat each bunch is considered as an independentoscillator at the betatron frequency and the motion ofeach bunch is controlled individually. The task of thefeedback system is to correct the trajectory of each bunchwith a transverse electromagnetic field in order to add adamping term to its equation of motion. The strength ofthe correction kick for each bunch can be derived fromthe position error of the same bunch detected in anotherlocation of the ring.Figure 1 shows the block diagram of the ELETTRAtransverse multi-bunch feedback system [1].The position of the 432 bunches is detected by the fourbuttons of a Beam Position Monitor followed by a"hybrid network" that produces the x, y and I signals.The wide-band signals are demodulated by the"RF front-end" giving a base-band 0÷250 MHz signalwhich represents the position error of the bunchespassing through the BPM at the frequency of 500 MHz.This analog signal is sampled by a fast 500 Msample/sA/D converter. The samples are passed to a bank of DSPs(Digital Signal Processor) that calculate the correctionsand these are converted to an analog signal by a D/Aconverter at 500 Msample/s. This signal represents thecorrections that have to be applied to the electronbunches as they pass through the kicker. A RF poweramplifier supplies the necessary power to drive thekicker.2 PROCESSING ELECTRONICSARCHITECTUREAfter a thorough analysis of the computing powerrequired to process in real-time this unprecedentedamount of data (500 Msample/s), a parallel architecturemade of a bank of DSPs has been adopted. The TexasInstruments TMS320C6201 fixed point DSP has beenchosen. The choice of using a modular architecture basedon VME boards interfaced through standard high-speedcommunication paths allows flexibility andupgradability.The block diagram of the system is shown in figure 2.The A/D Converter (ADC) VME board samples theanalog signal at 500 Msample/s with 8-bit resolution.The first de-multiplexing of the data is performed onboard into six 32-bit data paths which are individuallyconnected to a FPDP (Front Panel Data Port) parallelDACBoardADCBoardAnalogINDSPBoardDSPFPDPDEMUXDEMUXMUXA/D32DSPDSPDSPMUXFPDP32D/AAnalogOUTClockDistributionModule TriggerGeneratorBoardClock ClockStart-ADC Start-DACExternalProgrammingExternalProgramming500MHzStorageRingRFFigure 1: Block diagram of the Transverse Multi-Bunch Feedback SystemA/D D/ADigitalProcessingRFFront-EndRFAmplifierHybridNetworkKickerBPMWidebandSignalBaseband Signal(0÷250 MHz)Correction Signal(0÷250 MHz)DSPFigure 2: Block diagram of the processing electronicsInternational Conference on Accelerator and Large Experimental Physics Control Systems255International Conference  Accel rator and L rge Experim ntal Physics Control Systems, 1999, Trieste, Italyinterface. Each FPDP is connected to a DSP board bymeans of an Interface Module that distributes theincoming data to its four DSPs. After processing, thedata from the DSPs are multiplexed following asymmetric scheme and are converted to analog by the 8-bit D/A Converter (DAC) VME board. The wholeprocess is synchronized by timing signals provided by thetiming electronics.The transverse feedback processing electronics will bemade of two VME chassis: one for the horizontal andone for the vertical plane. Each of them will host oneADC board, one DAC board, six DSP boards equippedwith the Interface Module, and one timing board. TheVME bus will be used to initialize, control and monitorthe system and to download the programs into the DSPboards.The ADC board, DAC board and DSP boards arecommercial-of-the-shelf components. The InterfaceModule and the timing electronics are in-housedevelopments.3 ADC AND DAC BOARDSThe ADC and DAC boards are respectively theADC750 and DAC750 models from Celerity SystemIncorporated. These boards perform A/D and D/Aconversions at up to 750 Msample/s with 8-bit resolution.For the Feedback System we operate them at the bunchcrossing frequency, i.e. 500 Msample/s, using a clockderived from the main RF signal and connected to theexternal clock inputs.The 8-bit data out of the A/D converter of the ADCboard are first stacked in 32-bit words and thensequentially distributed to the six FPDP output ports. Thesix ports work at 20.8 MHz.An external trigger signal (Start-ADC) provided by thetiming electronics starts the conversion and the de-multiplexing process. Being the bunch number (432)divisible by 6 (number of FPDPs) times 4 (number ofbyte per FPDP word), each FPDP port always carries thesamples relative to the same group of 72 bunches. This isthe basic principle of the bunch-by-bunch feedback,where each group of bunches is processed always by thesame DSP on the same DSP board.In the DAC board the input data from the FPDP portsare treated in a complementary way with respect to theADC board. The FPDP data are multiplexed into one 8-bit path and transformed to analog by the D/A converter.In addition, some data buffering is performed by the useof FIFOs to de-couple from possible variations in theprocessing chain delays.An external trigger signal (Start-DAC) provided by thetiming electronics starts the multiplexing and theconversion process. Start-DAC is generated with aprogrammable delay relative to the Start-ADC in order tomake the correction kicks synchronous with the bunchespassing through the kicker.4 DSP BOARD AND INTERFACEMODULEThe DSP board adopted is the Pentek model 4290.Figure 3 shows the DSP board block diagram. The fourTI-TMS320C6201 DSPs communicate with themezzanine Interface Module via high-speed bi-directional FIFOs (BI-FIFO). The DSP use the BI-FIFOto acquire the bunch position samples and put thecorrection samples after processing.Each of the DSPs is in charge of processing thesamples of a given group of bunches. The InterfaceBoard receives 32-bit words from the FPDP Input andwrites them to the BI-FIFOs of the DSPs to which theyare specifically assigned. At the same time it reads theBI-FIFOs and sends out the data words to the FPDPOutput. The Interface Module acts as a programmable bi-directional commutator: the switching rules are definedin a table where, for each of the incoming/outgoingFPDP words relative to one machine turn, thedestination/source DSP is specified. As more than onedestination can be specified for each of the input words,they can be sent e.g. both to the first DSP and to one ofthe other three. This allows using one DSP for beamdiagnostics and the other three for the actual feedback.The table is downloaded on the Interface Module at thetime of system initialization.The TI TMS320C6201 is a fixed point DSP clocked at200 MHz (5 ns instruction cycle). The VLIW (Very LongInstruction Word) architecture allows to execute up toeight instructions every cycle. The challenging problemis to be able to execute all of the necessary operations inone revolution period (864 ns). With a highly optimizedcode written in Assembler, the time needed to execute allthe operations for a 5-tap Finite Impulse Response (FIR)filter is 600 ns, that is shorter than the revolution time.Another critical issue is the data transfer between theGlobalMemoryVMEInterfaceDSP BoardInterfaceModuleFPDPINFPDPOUTProgrammableLogicJ-TAGControllerExternal ProgrammingGlobalBusBIFIFODSP 0LocalMemoryMezzanineConnectorLocalBusBIFIFODSP 1LocalMemoryMezzanineConnectorBIFIFODSP 2LocalMemoryMezzanineConnectorBIFIFODSP 3LocalMemoryMezzanineConnectorFigure 3: Block diagram of the DSP Board and theInterface Module256DSP and the BI-FIFO. Simulations carried out with themachine/feedback simulator show that the feedbackperformance degrades with betatron tune shift when thenumber of processing revolution periods increases.Therefore, the time the data remain in the DSP boardmust be minimized as well as any delay on everycomponent of the feedback chain. A thorough use of theBI-FIFO facilities, interrupts and Direct Memory Access(DMA) allows to transfer data in a very effective waywithout interference with the CPU.5 TIMING ELECTRONICSThe transverse feedback system relies on a very stricttiming. The A/D converter must sample the analogsignal synchronously to the bunch crossing at the BPMand the D/A converter must generate the analogcorrections in phase with the bunches passing throughthe kicker. Moreover, the Start-ADC and Start-DACtrigger signals must start the conversions in adeterministic and repeatable way with respect to thebunch structure to let every DSP work with a knowngroup of bunches. A new design has been undertaken tofulfil these requirements. It consists of a ClockDistribution Module and a Trigger Generator Board(figure 2).The Clock Distribution Module accepts a 500 MHzsinusoidal signal from the storage ring RF and generatestwo 500 MHz Differential ECL (DECL) signals whichare the clocks used by the ADC and DAC boards. Thephase of the two output signals can be independentlyprogrammed in a 5 ns range with 5 ps resolution.The Trigger Generator Board is a VME general-purpose timing board. For the transverse feedback systemit provides two DECL signals: Start-ADC and Start-DAC. By conveniently programming the board via theVME interface it is possible to place the rising edge ofthe two trigger signals in any position of the revolutionperiod with a resolution of 10 ps. The Start-DAC mustfollow the Start-ADC and the time between the two hasto take into account the delay of the data flowing fromthe ADC to the DAC board.6 SYSTEM FEATURESBeing the feedback core realized by softwareprograms, a high degree of flexibility in theimplementation of the control algorithms is provided.The basic requirements for the feedback algorithm areDC rejection and appropriate gain/phase at the betatronfrequency. A 3-tap FIR is the most simple digital filterwhich can be used. However, many features can be addedwhen a more complicated filter is implemented. Studieshave been carried out with the support of amachine/feedback simulator [1] using 5-tap FIR andInfinite Impulse Response (IIR) digital filters.The maximum RF power supplied by the amplifier canbe a limitation of the feedback performance when astrong cavity High Order Mode is excited. In order tofully exploit the available power, it can be convenient toincrease the open-loop feedback gain and to make thefeedback saturate when the oscillations are large. On theother hand, high gain can lead to a greater residual errorwhen the oscillation is damped. The possibility ofchanging the filter parameters on-the-fly when thefeedback is running allows to change the gain and/or thefilter type and apply the best algorithm in the differentphases of a mode damping.With a convenient programming of the DSPs, oneuncontrolled bunch can be used for betatron tunemeasurements while applying the feedback to the others.With the measured tune value it is possible to re-calculate the filter parameters and change them when thefeedback is running, thus compensating for machine tuneshifts.Thanks to the programmability of the DSPs and theInterface Module the same processing electronics will beused for the Swiss Light Source transverse feedbacksystem and may be adopted also for longitudinal multi-bunch feedback systems.7 STATUSA transverse bunch-by-bunch digital feedback systemhas been designed at ELETTRA for damping multi-bunch instabilities. The digital processing electronics isrealized by a programmable modular multi-processorarchitecture.The system mainly relies on standard COTScomponents. The ADC/DAC boards have been orderedwhile a sample DSP board is under test. The timingelectronics and the Interface Module are in-houseprojects: the first prototypes are foreseen by the end ofNovember.The feedback project is a collaboration with the SwissLight Source which is developing the kickers and the RFfront-end. The system will be installed andcommissioned at ELETTRA: the first tests are foreseenby the end of 1999.8 AKNOWLEDGEMENTSThe authors wish to thank the "Detector andInstrumentation Group" of the Experimental Divisionand the "Instrumentation Group" of the AcceleratorDivision for their contribution to the project through thedevelopment of the Interface Module and timingmodules.REFERENCES[1] D. Bulfone et al., "Design Considerations for theELETTRA Transverse Multi-bunch Feedback", PAC'99, New York, March 1999.[2] M. Lonza, "Theory of the Transverse Multi-bunchFeedback at ELETTRA", ST Technical Note: to bepublished.257

Digital Processing Electronics for the ELETTRA Transverse Multi-Bunch Feedback System

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