Experimental and Design effort to understand a wider sense of memory application

Magnetic Random-Access Memory (mRAM) is a more efficient, smaller, and less power-hungry memory device that can be implemented into computers. Using Magnetic Tunnel Junctions (MTJ) we store memory in devices that are far less complex than other types of memory with just the use of currents and magnetic fields changing the data. In collaboration with the System-on-Chip Extension Technologies (SoCET) and Computing Advances by Probabilistic Spin Logic (CAPSL) groups, we have been working on using the characteristics of MTJs to characterize available commercial mRAM devices so we can have a better understanding of the thresholds of the MTJs. The SoCET teams develops chips using elements of the basic architecture and machine learning optimization. The CAPSL team creates probabilistic bits (p-bits) for probabilistic computing using MTJs and the Boltzmann Machine. Combining these two teams together I can work with mRAM to take the knowledge of computer architecture and knowledge of MTJ to better characterize and test the mRAM. To conduct the testing of commercial mRAM devices, a System Verilog code for a memory controller is being developed to input the data into the mRAM and read the data. To characterize mRAM we will test it by straining it multiple ways such as heat, high magnetic fields, and varying magnetic fields. We will be able to characterize it by comparing the data written into the device to the data read from the device after it has been strained

Leveraging Signal Transfer Characteristics and Parasitics of Spintronic Circuits for Area and Energy-Optimized Hybrid Digital and Analog Arithmetic

While Internet of Things (IoT) sensors offer numerous benefits in diverse applications, they are limited by stringent constraints in energy, processing area and memory. These constraints are especially challenging within applications such as Compressive Sensing (CS) and Machine Learning (ML) via Deep Neural Networks (DNNs), which require dot product computations on large data sets. A solution to these challenges has been offered by the development of crossbar array architectures, enabled by recent advances in spintronic devices such as Magnetic Tunnel Junctions (MTJs). Crossbar arrays offer a compact, low-energy and in-memory approach to dot product computation in the analog domain by leveraging intrinsic signal-transfer characteristics of the embedded MTJ devices. The first phase of this dissertation research seeks to build on these benefits by optimizing resource allocation within spintronic crossbar arrays. A hardware approach to non-uniform CS is developed, which dynamically configures sampling rates by deriving necessary control signals using circuit parasitics. Next, an alternate approach to non-uniform CS based on adaptive quantization is developed, which reduces circuit area in addition to energy consumption. Adaptive quantization is then applied to DNNs by developing an architecture allowing for layer-wise quantization based on relative robustness levels. The second phase of this research focuses on extension of the analog computation paradigm by development of an operational amplifier-based arithmetic unit for generalized scalar operations. This approach allows for 95% area reduction in scalar multiplications, compared to the state-of-the-art digital alternative. Moreover, analog computation of enhanced activation functions allows for significant improvement in DNN accuracy, which can be harnessed through triple modular redundancy to yield 81.2% reduction in power at the cost of only 4% accuracy loss, compared to a larger network. Together these results substantiate promising approaches to several challenges facing the design of future IoT sensors within the targeted applications of CS and ML

Spintronic Devices as P-Bits for Probabilistic Computing

Several beyond-CMOS computing technologies have emerged in the recent years to tackle the modern computing tasks that become intractable for Boolean logic based computation, performed on a von Neumann computer. The underlying philosophy in developing such technologies is to harness the natural physics of the computing elements to perform certain specialized computing tasks. One such beyond-CMOS computing paradigm- probabilistic computing is based on a “p-bit” that randomly fluctuates between 0 and 1, a behavior that is naturally mimicked by thermally unstable nanomagnets. A coupled network of such nanomagnets traverses through its collective states and is naturally guided towards the pre-designed low energy states. This property has been shown to be useful in providing hardware acceleration to a wide variety of problems in optimization, invertible logic, inference and machine learning. In order to develop practical circuits with p-bits, an efficient way to implement them in hardware by leveraging spintronics technology is required and forms the subject of this thesis. First, the experiments demonstrating the convergence of a weakly coupled nanomagnet network’s configuration towards the ground state of the associated Hamiltonian is shown. Next, it is demonstrated that by varying the interconnection strength and bias parameters in a two p-bit electrical circuit, Bayesian network building blocks can be implemented in hardware. Following this, a unique p-bit design based on the interaction of spin orbit torque on weak perpendicular anisotropy nanomagnets is presented and its interesting properties such as stochastic resonance, electrically tunable fluctuation rate and correlated fluctuations of two such devices are discussed. As related work, a prototype spin logic device is demon-strated using a composite stack of stable nanomagnets having perpendicular and in plane anisotropies. Finally, the development of a hybrid material stack with greatly improved giant spin Hall efficiency by incorporating W Se2 for energy efficient spin orbit torque switching of nanomagnets is presented