Optical Interconnection Architectures based on Microring Resonators

Abstract: Microring resonators are an interesting device to build integrated optical interconnects, but their asymmetric loss behavior could limit the scalability of classical optical interconnects. We present new interconnects able to increase scalability with limited complexity

TFTs as photodetectors for optical interconnects

In this work we are looking at the prospect of using poly-silicon based Thin Film Transistors (TFTs) as photodetectors for optical interconnects that can detect light effectively at 1100nm wavelength from silicon based Light Emitting Diodes (LEDs). These TFTs were fabricated from laser crystallized silicon and were characterized under darkness and illumination. The photosensitivities of these devices were limited due to the presence of aluminium as their gate electrode but have shown us the possibility of a new approach to photodetection

Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

A 160Gb/s (4x40) WDM O-band Tx subassembly using a 4-ch array of silicon rings co-packaged with a SiGe BiCMOS IC driver

We present a 400 (8×50) Gb/s-capable RM-based Si-photonic WDM O-band TxRx with 1.17nm channel spacing for high-speed optical interconnects and demonstrate successful 50Gb/s-NRZ TxRx operation achieving a ~4.5dB Tx extinction ratio under 2.15Vpp drive

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Optical computing: introduction by the guest editors to the feature in the 1 May 1988 issue

The feature in the 1 May 1988 issue of Applied Optics includes a collection of papers originally presented at the 1987 Lake Tahoe Topical Meeting on Optical Computing. These papers emphasize digital optical computing systems, optical interconnects, and devices for optical computing, but analog optical processing is considered as well