Design of Multistage Decimation Filters Using Cyclotomic Polynomials: Optimization and Design Issues

This paper focuses on the design of multiplier-less decimation filters suitable for oversampled digital signals. The aim is twofold. On one hand, it proposes an optimization framework for the design of constituent decimation filters in a general multistage decimation architecture. The basic building blocks embedded in the proposed filters belong, for a simple reason, to the class of cyclotomic polynomials (CPs): the first 104 CPs have a z-transfer function whose coefficients are simply {-1,0,+1}. On the other hand, the paper provides a bunch of useful techniques, most of which stemming from some key properties of CPs, for designing the proposed filters in a variety of architectures. Both recursive and non-recursive architectures are discussed by focusing on a specific decimation filter obtained as a result of the optimization algorithm. Design guidelines are provided with the aim to simplify the design of the constituent decimation filters in the multistage chain.Comment: Submitted to CAS-I, July 07; 11 pages, 5 figures, 3 table

Eigenfilters for the design of special transfer functions with applications in multirate signal processing

Based on the multistage approach, a design procedure is presented for finding a spectral factor of an mth-band filter and for designing multistage decimation filters. The proposed design method finds spectral factors of mth-band FIR (finite-impulse response) filters without direct computation, and yields filters with much higher attenuation than would be possible by conventional methods. Such mth-band filters are used in filter-bank designs, including perfect-reconstruction systems

Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain

In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature) with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel

STATE-OF-THE-ART DEVELOPMENTS IN ACCELERATOR CONTROLS AT THE APS * +

Abstract The performancerequirements of the Advanced Photon Source (APS) challenge the control system in a number of areas. This paper will review a few applications of advanced technology in the control and monitoring of the APS. The application of digital signal processors (DSPS) and techniques will be discussed, both from the perspective of a large distributed multiprocessor system and from that of embedded systems. In particular, two embedded applications will be highlighted, a beam position monitor processor and a DSP-based power supply controller. Fast data distribution is often a requirement. The application of a high-speed network based on reflective memory will also be discussed in the context of the APS global orbit feedback system. Timing systems provide opportunities to apply technologies such as high-speed logic and fiber optics. Examples of the use of these technologies will also be included. Fhlly, every modem accelerator control system of any size requires networking. Features of the APS accelerator controls network will be discussed