Statistical variability and reliability in nanoscale FinFETs

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics

Reduction of Line Edge Roughness (LER) in Interference-Like Large Field Lithography

Line edge roughness (LER) is seen as one of the most crucial challenges to be addressed in advanced technology nodes. In order to alleviate it, several options were explored in this work for the interference-like lithography imaging conditions. The most straight forward option was to scale interference lithography (IL) for large field integrated circuit (IC) applications. IL not only serves as a simple method to create high resolution period patterns, but, it also provides the highest theoretical contrast achievable compared to other optical lithography systems. Higher contrast yields a smaller transition region between the low and high intensity parts of the image, therefore, inherently lowers LER. Two of the challenges that would prohibit scaling IL for large field IC applications were addressed in this work: (1) field size limitations, and (2) magnification correction (i.e., pitch fine-tuning) ability. Experimental results showed less than 0.5 nm pitch adjustment capability using fused silica wedges mounted on rotational stages at 300 nm pitch pattern. A detailed discussion on maximum practical IL field size was outlined by considering the subsequent trim exposures and optical path difference effects between the interfering diffraction orders. The practical limit on the IL field size was assessed to be 10 mm for the conditions specified in this work. One of the contributors of LER is the mask absorber roughness. To mitigate it, two methods were explored that are also applicable to scanners working under interference-like conditions: (1) aerial image averaging via directional translation, and (2) pupil plane filtering. Experiments on pupil plane filtering approach were performed at Imec in Leuven, Belgium, on the ASML:NXT1950i scanner equipped with FlexWAVE wavefront manipulator. Utilizing an optimized phase filter at the pupil plane and a programmed roughness mask, the transfer of 200 nm roughness period to the wafer plane was eliminated. This mitigation effect was found to be strongly dependent on the focus

Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates

Photobase Generator Enabled Pitch Division: A Progress Report

Pitch division lithography (PDL) with a photobase generator (PBG) allows printing of grating images with twice the pitch of a mask. The proof-of-concept has been published in the previous paper[1, 2] and demonstrated by others[1]. Forty five nm half-pitch (HP) patterns were produced using a 90nm HP mask, but the image had line edge roughness (LER) that does not meet requirements. Efforts have been made to understand and improve the LER in this process. Challenges were summarized toward low LER and good performing pitch division. Simulations and analysis showed the necessity for an optical image that is uniform in the z direction in order for pitch division to be successful. Two-stage PBGs were designed for enhancement of resist chemical contrast. New pitch division resists with polymer-bound PAGs and PBGs, and various PBGs were tested. This paper focuses on analysis of the LER problems and efforts to improve patterning performance in pitch division lithography.Chemical Engineerin

A device-level characterization approach to quantify the impacts of different random variation sources in FinFET technology

A simple device-level characterization approach to quantitatively evaluate the impacts of different random variation sources in FinFETs is proposed. The impacts of random dopant fluctuation are negligible for FinFETs with lightly doped channel, leaving metal gate granularity and line-edge roughness as the two major random variation sources. The variations of Vth induced by these two major categories are theoretically decomposed based on the distinction in physical mechanisms and their influences on different electrical characteristics. The effectiveness of the proposed method is confirmed through both TCAD simulations and experimental results. This letter can provide helpful guidelines for variation-aware technology development

Polymer Dissolution Model: An Energy Adaptation Of The Critical Ionization Theory

The current scale of features size in the microelectronics industry has reached the point where molecular level interactions affect process fidelity and produce excursions from the continuum world like line edge roughness (LER). Here we present a 3D molecular level model based on the adaptation of the critical ionization (CI) theory using a fundamental interaction energy approach. The model asserts that it is the favorable interaction between the ionized part of the polymer and the developer solution which renders the polymer soluble. Dynamic Monte Carlo methods were used in the current model to study the polymer dissolution phenomenon. The surface ionization was captured by employing an electric double layer at the interface, and polymer motion was simulated using the Metropolis algorithm. The approximated interaction parameters, for different species in the system, were obtained experimentally and used to calibrate the simulated dissolution rate response to polymer molecular weight and developer concentration. The predicted response is in good agreement with experimental dissolution rate data. The simulation results support the premise of the CI theory and provide an insight into the CI model from a new prospective. This model may provide a means to study the contribution of development to LER and other related defects based on molecular level interactions between distinct components in the polymer and the developer.Chemical Engineerin

Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with σVT values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD (σVT= 8 mV) and minimally influenced by the GER (σVT ≈ 4 mV). The variability of NS FETs makes them strong candidates to replace FinFETs