Evaluation Method for SDN Network Effectiveness in Next Generation Cellular Networks

5G mobile technology will become the new revolution in the mobile communication market. The new networks will focus on significantly improving the quality of service. The basis for their construction will form SDN networks. Therefore, the work analyzed the advantages and disadvantages of two SDN implementing methods. It was developed mathematical method to assess their complex effectiveness, which consider QoS requirements of implementing service through special weights for scalability, performance and packet delay. There were simulations of Overlay networks by using softswitches to verify the adequacy of the proposed method. The results showed that the use of SDN networks more efficiently by using IP networks for large volumes of traffic and with a large number of network equipment. Also, there were compared the approaches to build SDN management level architecture. Based on the studies and modeling we suggested to use distributed controller architecture because of its higher level of reliability

Traffic Management Applications for Stateful SDN Data Plane

The successful OpenFlow approach to Software Defined Networking (SDN) allows network programmability through a central controller able to orchestrate a set of dumb switches. However, the simple match/action abstraction of OpenFlow switches constrains the evolution of the forwarding rules to be fully managed by the controller. This can be particularly limiting for a number of applications that are affected by the delay of the slow control path, like traffic management applications. Some recent proposals are pushing toward an evolution of the OpenFlow abstraction to enable the evolution of forwarding policies directly in the data plane based on state machines and local events. In this paper, we present two traffic management applications that exploit a stateful data plane and their prototype implementation based on OpenState, an OpenFlow evolution that we recently proposed.Comment: 6 pages, 9 figure

MARS: Machine learning-based Adaptable and Robust network management for Software-defined networks

MARS is an adaptable and robust network management approach using machine learning while considering the control plane architecture for software-defined networks. Project goal is enhancing the network resource utilization and SDN scalability

High level synthesis of RDF queries for graph analytics

In this paper we present a set of techniques that enable the synthesis of efficient custom accelerators for memory intensive, irregular applications. To address the challenges of irregular applications (large memory footprint, unpredictable fine-grained data accesses, and high synchronization intensity), and exploit their opportunities (thread level parallelism, memory level parallelism), we propose a novel accelerator design that employs an adaptive and Distributed Controller (DC) architecture, and a Memory Interface Controller (MIC) that supports concurrent and atomic memory operations on a multi-ported/multi-banked shared memory. Among the multitude of algorithms that may benefit from our solution, we focus on the acceleration of graph analytics applications and, in particular, on the synthesis of SPARQL queries on Resource Description Framework (RDF) databases. We achieve this objective by incorporating the synthesis techniques into Bambu, an Open Source high-level synthesis tools, and interfacing it with GEMS, the Graph database Engine for Multithreaded Systems. The GEMS' front-end generates optimized C implementations of the input queries, modeled as graph pattern matching algorithms, which are then automatically synthesized by Bambu. We validate our approach by synthesizing several SPARQL queries from the Lehigh University Benchmark (LUBM)

빠른 성능조건 만족을 위한 임계경로를 고려하는 상위 수준 합성

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 최기영.Rapid advancement of process technology enables designers to integrate various functions onto a single chip and to realize diverse requirements of customers, but productivity of system designers has improved too slowly to make optimal design in time-to-market. Since designing at higher levels of abstraction reduces the number of design instances to be considered to acquire an optimal design, it improves quality of system as well as reduces design time and cost. High-level synthesis, which maps behavioral description models to register-transfer models, can improve design productivity drastically, and thus, it has been one of the important issues in electronic system level design. Centralized controllers commonly used in high-level synthesis often require long wires and cause high load capacitance, and that is why critical paths typically occur on paths from controllers to data registers instead of paths from data registers to data registers. However, conventional high-level synthesis has focused on delays within a datapath, making it difficult to solve the timing closure problem during physical synthesis. This thesis presents hardware architecture with a distributed controller, which makes the timing closure problem much easier. A novel critical-path-aware high-level synthesis flow is also presented for synthesizing such hardware through datapath partitioning, register binding, and controller optimization. We explore the design space related to the number of partitions, which is an important design parameter for target architecture. According to our experiments, the proposed approach reduces the critical path delay excluding FUs by 29.3% and that including FUs by 10.0%, with 2.2% area overhead on average compared to centralized controller architecture. We also propose two approaches, clock gating and register constrained flow, to alleviate high peak current problem which is caused by the proposed approach. These approaches suppress the peak current overhead to keep it less than 3.6%.Chapter 1 Introduction 1 Chapter 2 Background 7 2.1 High-level Synthesis 7 2.2 Subtasks of High-level Synthesis 8 2.2.1 Operation Scheduling and FU Binding 8 2.2.2 Register Binding 10 2.2.3 Controller Synthesis 11 2.2.4 Functional Pipelining Technique for High-level Synthesis 11 2.3 Centralized Controller Architecture 12 2.4 Design Closure Problem in High-level Synthesis 15 2.5 Thesis Contribution 18 Chapter 3 Target Architecture and Overall flow 21 3.1 Target Architecture 21 3.2 Overall flow 23 Chapter 4 Critical-Path-Aware Datapath Partitioning 27 4.1 Introduction 27 4.2 Problem Formulation 30 4.3 Proposed Algorithm 32 4.4 Exploring Design Space for the Number of Partitions 36 Chapter 5 Critical-Path-Aware Register Binding 39 5.1 Introduction 39 5.2 Problem Formulation 40 5.3 Proposed Algorithm 43 Chapter 6 Critical-Path-Aware Controller Optimization 49 6.1 Introduction 49 6.2 Problem Formulation 50 6.3 Proposed Algorithm 55 Chapter 7 Evaluation 63 7.1 Experimental Setup 63 7.2 Design Parameters and Computation Time 66 7.3 Analysis Critical Path Delay on Distributed Controller Architecture 68 7.4 Analysis of Performance and Area 70 7.5 Energy Consumption 78 7.6 Analysis on Register Overhead 80 7.6.1 Clock Gating Approach 81 7.6.2 Register Constrained Approach 84 7.6.3 Combined Approach 86 7.7 Join to Conventional Optimization Techniques on HLS 87 7.8 Comparison with DRFM Binding Approach 87 Chapter 8 Conclusion and Future Work 89 8.1 Summary 89 8.2 Future Work 90 Bibliography 93 Abstract in Korean 103Docto

Implementasi Dynamic Switch Migration pada Controller Terdistribusi di Software Defined Network.

Software Defined Network merupakan teknologi yang dapat mengelola jaringan skala besar dengan memisahkan control plane dan data plane. Pengaturan jaringan dilakukan secara terpusat logically centralized oleh controller. ketika sebuah controller mengalami kelebihan load dan terjadi Single Point of Failure maka kinerja jaringan akan terganggu. Software Defined Network dapat mengatasi masalah tersebut dengan mengimplementasikan arsitektur Multiple Distributed Controller menggunakan metode Dynamic Switch Migration. Arsitektur Multiple Distributed Controller dalam penelitian ini menggunakan dua buah controller dengan peran Master dan Slave. Melalui simulasi menggunakan arsitektur Multiple Distributed Controller telah diuji kemampuan mekanisme Dynamic Switch Migration dalam menangani masalah kelebihan load pada controller dengan memindahkan sebagian switch dari controller master ke controller slave dan masalah Single Point of Failure dengan memindahkan seluruh switch controller master ke Controller slave. Kata kunci: Software Defined Network, Dynamic Switch Migration,Multiple Distributed Controller, kelebihan load,controller slave,controller maste

On the latency and jitter evaluation of software defined networks

Conventional networking devices require that each is programmed with different rules to perform specific collective tasks. Next generation networks are required to be elastic, scalable and secured to connect millions of heterogeneous devices. Software defined networking (SDN) is an emerging network architecture that separates control from forwarding devices. This decoupling allows centralized network control to be done network-wide. This paper analyzes the latency and jitter of SDN against a conventional network. Through simulation, it is shown that SDN has an average three times lower jitter and latency per packet that translate to improved throughput under varying traffic conditions