213,665 research outputs found

    ATLAS IBL Pixel Upgrade

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    The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reducing the pixel size and of the material budget. Three different promising sensor technologies (planar-Si, 3D-Si and diamond) are currently under investigation for the pixel detector. An overview of the project with particular emphasis on pixel module is presented in this paper.Comment: 3 pages, 3 figures, presented at the 12th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD10) 7 - 10 June 2010, Siena (IT). Accepted by Nuclear Physics B (Proceedings Supplements) (2011

    Results from the Commissioning of the ATLAS Pixel Detector with Cosmic data

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    The ATLAS pixel detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. With approximately 80 million readout channels, the ATLAS silicon pixel detector is a high-acceptance, high-resolution, low-noise tracking device. Providing the desired refinement in charged track pattern recognition capability in order to meet the stringent track reconstruction requirements, the pixel detector largely defines the ability of ATLAS to effectively resolve primary and secondary vertices and perform efficient flavor tagging essential for discovery of new physics. Being the last sub-system installed in ATLAS by July 2007, the pixel detector was successfully connected, commissioned, and tested in situ while meeting an extremely tight schedule, and was ready to take data upon the projected turn-on of the LHC. Since fall 2008, the pixel detector has been included in the combined ATLAS detector operation, collecting cosmic muon data. Details from the pixel detector installation and commissioning, as well as details on calibration procedures and the results obtained with collected cosmic data, are presented along with a summary of the detector status.Comment: To be published in the proceedings of DPF-2009, Detroit, MI, July 2009, eConf C090726. Contents: 9 pages, 13 figures, 9 reference

    Measurement of the energy resolution and calibration of hybrid pixel detectors with GaAs:Cr sensor and Timepix readout chip

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    This paper describes an iterative method of per-pixel energy calibration of hybrid pixel detectors with GaAs:Cr sensor and Timepix readout chip. A convolution of precisely measured spectra of characteristic X-rays of different metals with the resolution and the efficiency of the pixel detector is used for the calibration. The energy resolution of the detector is also measured during the calibration. The use of per-pixel calibration allows to achieve a good energy resolution of the Timepix detector with GaAs:Cr sensor: 8% and 13% at 60 keV and 20 keV, respectively

    Optical Readout in a Multi-Module System Test for the ATLAS Pixel Detector

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    The innermost part of the ATLAS experiment at the LHC, CERN, will be a pixel detector. The command messages and the readout data of the detector are transmitted over an optical data path. The readout chain consists of many components which are produced at several locations around the world, and must work together in the pixel detector. To verify that these parts are working together as expected a system test has been built up. In this paper the system test setup and the operation of the readout chain is described. Also, some results of tests using the final pixel detector readout chain are given.Comment: 6 pages, 10 figures, Pixel 2005 proceedings preprin

    The new radiation-hard optical links for the ATLAS pixel detector

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    The ATLAS detector is currently being upgraded with a new layer of pixel based charged particle tracking and a new arrangement of the services for the pixel detector. These upgrades require the replacement of the opto-boards previously used by the pixel detector. In this report we give details on the design and production of the new opto-boards.Comment: Presentation at the DPF 2013 Meeting of the American Physical Society Division of Particles and Fields, Santa Cruz, California, August 13-17, 201

    A low mass pixel detector upgrade for CMS

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    The CMS pixel detector has been designed for a peak luminosity of 10^34cm-2s-1 and a total dose corresponding to 2 years of LHC operation at a radius of 4 cm from the interaction region. Parts of the pixel detector will have to be replaced until 2015. The detector performance will be degraded for two reasons: radiation damage of the innermost layers and the planned increase of the LHC peak luminosity by a factor of 2-3. Based on the experience in planning, constructing and commissioning of the present pixel detector, we intend to upgrade the whole pixel detector in 2015. The main focus is on lowering the material budget and adding more tracking points. We will present the design of a new low mass pixel system consisting of 4 barrel layers and 3 end cap disks on each side. The design comprises of thin detector modules and a lightweight mechanical support structure using CO2 cooling. In addition, large efforts have been made to move material from the services out of the tracking region.Comment: 10 pages, 10 figures, Proceeding of RD09 - 9th International Conference on Large Scale Applications and Radiation Hardness of Semiconductor Detectors 30 September - 2 October 2009, Florence, Ital

    Status of the CMS Phase I Pixel Detector Upgrade

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    A new pixel detector for the CMS experiment is being built, owing to the instantaneous luminosities anticipated for the Phase I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking while featuring a significantly reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and comprises a low-threshold comparator. These improvements allow the new pixel detector to sustain and improve the efficiency of the current pixel tracker at the increased requirements imposed by high luminosities and pile-up. This contribution gives an overview of the design of the upgraded pixel detector and the status of the upgrade project, and presents test beam performance measurements of the production read-out chip.Comment: Presented at the 10th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors, Xi'an, Chin

    Nano-optical observation of cascade switching in a parallel superconducting nanowire single photon detector

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    The device physics of parallel-wire superconducting nanowire single photon detectors is based on a cascade process. Using nano-optical techniques and a parallel wire device with spatially-separate pixels we explicitly demonstrate the single- and multi-photon triggering regimes. We develop a model for describing efficiency of a detector operating in the arm-trigger regime. We investigate the timing response of the detector when illuminating a single pixel and two pixels. We see a change in the active area of the detector between the two regimes and find the two-pixel trigger regime to have a faster timing response than the one-pixel regime.Comment: 11 pages, 2 figure

    The ONSEN Data Reduction System for the Belle II Pixel Detector

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    We present an FPGA-based online data reduction system for the pixel detector of the future Belle II experiment. The occupancy of the pixel detector is estimated at 3 %. This corresponds to a data output rate of more than 20 GB/s after zero suppression, dominated by background. The Online Selection Nodes (ONSEN) system aims to reduce the background data by a factor of 30. It consists of 33 MicroTCA cards, each equipped with a Xilinx Virtex-5 FPGA and 4 GiB DDR2 RAM. These cards are hosted by 9 AdvancedTCA carrier boards. The ONSEN system buffers the entire output data from the pixel detector for up to 5 seconds. During this time, the Belle II high-level trigger PC farm performs an online event reconstruction, using data from the other Belle II subdetectors. It extrapolates reconstructed tracks to the layers of the pixel detector and defines regions of interest around the intercepts. Based on this information, the ONSEN system discards all pixels not inside a region of interest before sending the remaining hits to the event builder system. During a beam test with one layer of the pixel detector and four layers of the surrounding silicon strip detector, including a scaled-down version of the high-level trigger and data acquisition system, the pixel data reduction using regions of interest was exercised. We investigated the data produced in more than 20 million events and verified that the ONSEN system behaved correctly, forwarding all pixels inside regions of interest and discarding the rest.Comment: 7 pages, 10 figure
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