FPGA Design Techniques for Stable Cryogenic Operation

In this paper we show how a deep-submicron FPGA can be modified to operate at extremely low temperatures through modifications in the supporting hardware and in the firmware programming it. Though FPGAs are not designed to operate at a few Kelvin, it is possible to do so on virtue of the extremely high doping levels found in deep-submicron CMOS technology nodes. First, any PCB component, that does not conform with this requirement, is removed. Both the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad-hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA chip. The FPGA is powered with a supply at several meters distance, causing significant IR drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.Comment: The following article has been submitted to Review of Scientific Instruments. If it is published, it will be available on http://rsi.aip.or

Low Noise and High Photodetection Probability SPAD in 180 nm Standard CMOS Technology

A square shaped, low noise and high photo-response single photon avalanche diode suitable for circuit integration, implemented in a standard CMOS 180 nm high voltage technology, is presented. In this work, a p+ to shallow n-well junction was engineered with a very smooth electric field profile guard ring to attain a photo detection probability peak higher than 50% with a median dark count rate lower than 2 Hz/μm2 when operated at an excess bias of 4 V. The reported timing jitter full width at half maximum is below 300 ps for 640 nm laser pulses