Brain-Inspired Computing

This open access book constitutes revised selected papers from the 4th International Workshop on Brain-Inspired Computing, BrainComp 2019, held in Cetraro, Italy, in July 2019. The 11 papers presented in this volume were carefully reviewed and selected for inclusion in this book. They deal with research on brain atlasing, multi-scale models and simulation, HPC and data infra-structures for neuroscience as well as artificial and natural neural architectures

Towards brain-inspired computing

We present introductory considerations and analysis toward computing applications based on the recently introduced deterministic logic scheme with random spike (pulse) trains [Phys. Lett. A 373 (2009) 2338-2342]. Also, in considering the questions, "Why random?" and "Why pulses?", we show that the random pulse based scheme provides the advantages of realizing multivalued deterministic logic. Pulse trains are realized by an element called orthogonator. We discuss two different types of orthogonators, parallel (intersection-based) and serial (demultiplexer-based) orthogonators. The last one can be slower but it makes sequential logic design straightforward. We propose generating a multidimensional logic hyperspace [Physics Letters A 373 (2009) 1928-1934] by using the zero-crossing events of uncorrelated Gaussian electrical noises available in the chips. The spike trains in the hyperspace are non-overlapping, and are referred to as neuro-bits. To demonstrate this idea, we generate 3-dimensional hyperspace bases using 2 Gaussian noises as sources for neuro-bits, respectively. In such a scenario, the detection of different hyperspace basis elements may have vastly differing delays. We show that it is possible to provide an identical speed for all the hyperspace bases elements using correlated noise sources, and demonstrate this for the 2 neuro-bits situations. The key impact of this paper is to demonstrate that a logic design approach using such neuro-bits can yield a fast, low power processing and environmental variation tolerant means of designing computer circuitry. It also enables the realization of multi-valued logic, significantly increasing the complexity of computer circuits by allowing several neuro-bits to be transmitted on a single wire.Comment: 10 page

Author correction: Enabling controlling complex networks with local topological information

Correction to: Scientific Reports https://doi.org/10.1038/s41598-018-22655-5, published online 15 March 2018. The Acknowledgements section in this Article is incomplete.The work was partially supported by National Science Foundation of China (61603209, 61327902), and Beijing Natural Science Foundation (4164086), and the Study of Brain-Inspired Computing System of Tsinghua University program (20151080467), and SuZhou-Tsinghua innovation leading program 2016SZ0102, and Ministry of Education, Singapore, under contracts RG28/14, MOE2014-T2-1-028 and MOE2016-T2-1-119. Part of this work is an outcome of the Future Resilient Systems project at the Singapore-ETH Centre (SEC), which is funded by the National Research Foundation of Singapore (NRF) under its Campus for Research Excellence and Technological Enterprise (CREATE) program. (61603209 - National Science Foundation of China; 61327902 - National Science Foundation of China; 4164086 - Beijing Natural Science Foundation; 20151080467 - Study of Brain-Inspired Computing System of Tsinghua University program; 2016SZ0102 - SuZhou-Tsinghua innovation leading program; RG28/14 - Ministry of Education, Singapore; MOE2014-T2-1-028 - Ministry of Education, Singapore; MOE2016-T2-1-119 - Ministry of Education, Singapore; National Research Foundation of Singapore (NRF) under its Campus for Research Excellence and Technological Enterprise (CREATE) program)Published versio

Brain-inspired computing with fluidic iontronic nanochannels

The unparalleled energy efficiency of the brain is driving researchers to seek out new brain-inspired (neuromorphic) computing paradigms. Artificial aqueous ion channels are emerging as an exciting new platform for neuromorphic computing, representing a departure from conventional solid-state devices by directly mimicking the fluidic ion transport found in the brain. However, despite recent interest, a tangible demonstration of neuromorphic computing remains a challenge. Here we successfully perform neuromorphic reservoir computing using easy to fabricate tapered microchannels that embed a conducting network of fluidic nanochannels between colloids, which we show to be a novel memristor (memory resistor). Remarkably, a wide range of typical conductance memory timescales can easily be achieved by constructing channels of different length, a unique and highly desirable feature. This work is inspired and supported by a new theoretical model, which stems directly from traditional diffusion-conduction equations and shows excellent agreement with the experiments, predicting the features and relevant parameters presented here. Our results represent a fundamental step in realising the promise of ion channels as a new platform to emulate the rich aqueous dynamics of the brain

Memristive crossbar arrays for brain-inspired computing

While the speed-energy efficiency of traditional digital processors approach a plateau because of limitations in transistor scaling and the von Neumann architecture, computing systems augmented with emerging devices such as memristors offer an attractive solution. A memristor, also known as a resistance switch, is an electronic device whose internal resistance state is dependent on the history of the current and/or voltage it has experienced. With their working mechanisms based on ion migration, the switching dynamics and electrical behavior of memristors closely resemble those of biological synapses and neurons. Because of its small size and fast switching speed, a memristor consumes a small amount of energy to update the internal state (training). Built into large-scale crossbar arrays, memristors perform in-memory computing by utilizing physical laws, such as Ohm’s law for multiplication and Kirchhoff’s current law for accumulation. The current readout at all columns (inference) is finished simultaneously regardless of the array size, offering a huge parallelism and hence superior computing throughput. The ability to directly interface with analog signals from sensors, without analog/digital conversion, could further reduce the processing time and energy overhead. We developed memristive devices based on foundry compatible materials such as silicon oxide and halfnium oxide [1,2]. We demonstrated two nanometer scalability [3] and eight layer stackbility [4] with these devices. Furthermore, we integrated the halfnium oxide memristors into large analog crossbar arrays for analog signal and image processing [5], and the implemented multilayer memristor neural networks for machine learning applications [6,7]. The crossbar arrays were also used for other applications such as hardware security [8]. References: C. Li, et al. 3-Dimensional Crossbar Arrays of Self-rectifying Si/SiO2/Si Memristors , Nature Communications 8, 15666(2017). H. Jiang, et al. Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO2 Memristor , Scientific Reports 6, 28525(2016). S. Pi, et al. Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension , Nature Nanotechnology 14, 35-39(2019). P. Lin, et al. “Three-Dimensional Memristor Circuits as Complex Neural Networks”. Under review (2019). C. Li, et al. Analogue signal and image processing with large memristor crossbars , Nature Electronics 1, 52-59 (2018). C. Li, et al. Efficient and self-adaptive in-situ learning in multilayer memristor neural networks , Nature Communications 9, 2385 (2018). C. Li, et al. Long short-term memory networks in memristor crossbar arrays , Nature Machine Intelligence 1, 49-57(2019). H. Jiang, et al. A provable key destruction scheme based on memristive crossbar arrays , Nature Electronics 1, 548-554(2018)

Brain-inspired computing needs a master plan

New computing technologies inspired by the brain promise fundamentally different ways to process information with extreme energy efficiency and the ability to handle the avalanche of unstructured and noisy data that we are generating at an ever-increasing rate. To realize this promise requires a brave and coordinated plan to bring together disparate research communities and to provide them with the funding, focus and support needed. We have done this in the past with digital technologies; we are in the process of doing it with quantum technologies; can we now do it for brain-inspired computing

Brain inspired computing networks for smart building monitoring

The intelligent sensor systems capable of measuring a wide range of building conditions remotely, and in a real-time manner can reveal useful information on the overall quality of services offered in the maintenance and reliability of building space

A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing

Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are incompatible with memristor synapses, or used extra training circuitry thus eliminating much of the density advantages gained by using memristors, or were energy inefficient. Here we describe a novel CMOS spiking leaky integrate-and-fire neuron circuit. Building on a reconfigurable architecture with a single opamp, the described neuron accommodates a large number of memristor synapses, and enables online spike timing dependent plasticity (STDP) learning with optimized power consumption. Simulation results of an 180nm CMOS design showed 97% power efficiency metric when realizing STDP learning in 10,000 memristor synapses with a nominal 1M{\Omega} memristance, and only 13{\mu}A current consumption when integrating input spikes. Therefore, the described CMOS neuron contributes a generalized building block for large-scale brain-inspired neuromorphic systems.Comment: This is a preprint of an article accepted for publication in International Joint Conference on Neural Networks (IJCNN) 201