Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C.

III-V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III-Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)-coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III-Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics

Diameter-Dependent Electron Mobility of InAs Nanowires

Temperature-dependent I-V and C-V spectroscopy of single InAs nanowire field-effect transistors were utilized to directly shed light on the intrinsic electron transport properties as a function of nanowire radius. From C-V characterizations, the densities of thermally-activated fixed charges and trap states on the surface of untreated (i.e., without any surface functionalization) nanowires are investigated while enabling the accurate measurement of the gate oxide capacitance; therefore, leading to the direct assessment of the field-effect mobility for electrons. The field-effect mobility is found to monotonically decrease as the radius is reduced to sub-10 nm, with the low temperature transport data clearly highlighting the drastic impact of the surface roughness scattering on the mobility degradation for miniaturized nanowires. More generally, the approach presented here may serve as a versatile and powerful platform for in-depth characterization of nanoscale, electronic materials

Hybrid core-multishell nanowire forests for electrical connector applications

Electrical connectors based on hybrid core-multishell nanowire forests that require low engagement forces are demonstrated. The physical binding and electrical connectivity of the nanowire electrical connectors arise from the van der Waals interactions between the conductive metallic shells of the engaged nanowire forests. Specifically, the nanofibrillar structure of the connectors causes an amplification of the contact area between the interpenetrating nanowire arrays, resulting in strong adhesion with relatively low interfacial resistance. The nanowire electrical connectors may enable the exploration of a wide range of applications involving reversible assembly of micro- and macroscale components with built-in electrical interfacing.open151

Metal-catalyzed crystallization of amorphous carbon to graphene

Metal-catalyzed crystallization of amorphous carbon to graphene by thermal annealing is demonstrated. In this "limited source" process scheme, the thickness of the precipitated graphene is directly controlled by the thickness of the initial amorphous carbon layer. This is in contrast to chemical vapor deposition processes, where the carbon source is virtually unlimited and controlling the number of graphene layers depends on the tight control over a number of deposition parameters. Based on the Raman analysis, the quality of graphene is comparable to other synthesis methods found in the literature, such as chemical vapor deposition. The ability to synthesize graphene sheets with tunable thickness over large areas presents an important progress toward their eventual integration for various technological applications.open826

Room temperature multiplexed gas sensing using chemical-sensitive 3.5-nm-thin silicon transistors

There is great interest in developing a low-power gas sensing technology that can sensitively and selectively quantify the chemical composition of a target atmosphere. Nanomaterials have emerged as extremely promising candidates for this technology due to their inherent low-dimensional nature and high surface-to-volume ratio. Among these, nanoscale silicon is of great interest because pristine silicon is largely inert on its own in the context of gas sensing, unless functionalized with an appropriate gas-sensitive material. We report a chemical-sensitive field-effect transistor (CS-FET) platform based on 3.5-nm-thin silicon channel transistors. Using industry compatible processing techniques, the conventional electrically active gate stack is replaced by an ultrathin chemical-sensitive layer that is electrically conconducting and coupled to the 3.5-nm-thin silicon channel. We demonstrate a low-power, sensitive, and selective multiplexed gas sensing technology using this platform by detecting H_2S, H_2, and NO_2 at room temperature for environment, health, and safety in the oil and gas industry, offering significant advantages over existing technology. Moreover, the system described here can be readily integrated with mobile electronics for distributed sensor networks in environmental pollution mapping and personal air-quality monitors

Quantum Size Effects on the Chemical Sensing Performance of Two-Dimensional Semiconductors

We investigate the role of quantum confinement on the performance of gas sensors based on two-dimensional InAs membranes. Pd-decorated InAs membranes configured as H2 sensors are shown to exhibit strong thickness dependence, with ~100x enhancement in the sensor response as the thickness is reduced from 48 to 8 nm. Through detailed experiments and modeling, the thickness scaling trend is attributed to the quantization of electrons which favorably alters both the position and the transport properties of charge carriers; thus making them more susceptible to surface phenomena

Ultrathin compound semiconductor on insulator layers for high performance nanoscale transistors

Over the past several years, the inherent scaling limitations of electron devices have fueled the exploration of high carrier mobility semiconductors as a Si replacement to further enhance the device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied, combining the high mobility of III-V semiconductors and the well-established, low cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored. Besides complexity, high defect densities and junction leakage currents present limitations in the approach. Motivated by this challenge, here we utilize an epitaxial transfer method for the integration of ultrathin layers of single-crystalline InAs on Si/SiO2 substrates. As a parallel to silicon-on-insulator (SOI) technology14,we use the abbreviation "XOI" to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsOx layer (~1 nm thick). The fabricated FETs exhibit an impressive peak transconductance of ~1.6 mS/{\mu}m at VDS=0.5V with ON/OFF current ratio of greater than 10,000 and a subthreshold swing of 107-150 mV/decade for a channel length of ~0.5 {\mu}m

Formation of Iron Silicide Quantum Dots on Si (001)

[[abstract]]中華民國顯微鏡學會第21屆年會暨第23屆學術研討會[[fileno]]202_JA01_2003_n10_p3