Survey of oral hygiene behaviour, knowledge and oral hygiene status among Hong Kong adults : a pilot study

Objectives: To study the correlation between oral health behaviour and knowledge with respect to the oral hygiene status of Hong Kong Chinese adults. Materials and methods: Subject selection was by convenience sampling. A total of four outreach visits were arranged in March 2015. The participants’ oral health behavior and knowledge were evaluated through a self-reported questionnaire, while existing oral conditions were recorded following clinical examination using Visible Plaque Index (VPI) and Gingival Bleeding Index (GBI). Data analysis was carried out using SPSS on results obtained from the questionnaire as well as clinical examination. Results: A total of 147 subjects participated in this research project, of which 72% (103/147) were female while 28% (44/147) were male. Male subjects had statistically significantly higher mean VPI scores compared to female subjects interproximally, buccally and lingually (t-test, p<0.05). Furthermore, there exists a statistically significant negative correlation between oral health knowledge score (mean = 9.3, SD = 3.1) and VPI score (Pearson correlation test, p=0.025). Subjects who agreed accumulation of plaque or bacteria as a contributing factor to caries and periodontal diseases are statistically significantly lower than subjects who disagreed this statement in terms of mean VPI scores (53% vs 63%, t-test, p<0.05). Conclusion: Participants with better oral health knowledge who also recognized accumulation of plaque or bacteria as one of the contributing factors to dental caries and periodontal disease had better oral hygiene levels in terms of VPI.published_or_final_versio

An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch

Successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some applications, such as wireless sensor nodes, designing a low power and low energy ADC is one of the major challenges. For an SA-ADC, the dominant power dissipation sources are the comparator and the switching in the DAC capacitor array. We propose a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant and the least significant bits, and using two different capacitor arrays with unequal sizes to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced compared to the traditional switching methods. Experiments were carried out on a 10-bit SAR-ADC, designed using a TSMC 0.18μm CMOS process. HSPICE simulations show that a significant reduction in energy consumption is achieved using the proposed design. We also demonstrated the operation in a pipelined architecture to achieve higher throughput without the need of duplication of the DAC capacitor arrays. We also propose a novel architecture of an ultra-low offset comparator latch using on-chip calibration to compensate the process variation. The proposed technique compensates the variation in process parameters such as W/L, μCOX and threshold voltage independently by considering the intrinsic behavior of the MOS transistors without using power-hungry complicated circuits for measuring the transistor characteristics. Monte Carlo post-layout HSPICE simulations were carried out with 100 samples to evaluate the performance of the comparator latch. Experimental results show that when compared with state-of-the-art pre-amplifier-less architectures, the standard deviation of the input voltage offset is reduced by more than 75% over a range of 400mV difference in the common mode input voltage

Linear spaces of real matrices of constant rank

AbstractThe largest possible dimensions of linear spaces of real n×n matrices of constant rank n−1 (or n−2) are determined using topological K-theory and expressed in terms of Hurwitz-Radon numbers

Application of technical analysis on Hong Kong foreign exchangemarket

published_or_final_versionBusiness AdministrationMasterMaster of Business Administratio

Elastic analysis of coupled shear-walls subject to lateral loads

published_or_final_versionCivil EngineeringMasterMaster of Science in Engineerin

The influence of the outflow of the Pearl River on the waters of the South China Sea: with special reference tothe phosphate and nitrate content

published_or_final_versionBiochemistryMasterMaster of Scienc

A Novel Offset Cancellation Technique for Dynamic Comparator Latch

This paper presents a novel architecture of ultra-low offset comparator latch using on-chip calibration to compensate the process variation. The proposed technique compensates the variation in process parameters such as W/L, mu C-OX and threshold voltage independently by considering the intrinsic behavior of the MOS transistors without using power-hungry complicated circuits on measuring the transistor characteristics. Monte Carlo post-layout HSPICE simulations were carried out with 100 runs to evaluate the performance of the comparator latch. Experimental results show that when comparing with state-of-the-art pre-amplifier-less architectures, the standard deviation of the input voltage offset is reduced by more than 75% over a range of 400mV difference of the common mode input voltage

A low energy two-step successive approximation algorithm for ADC design

This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically reduced compared to the conventional switching methods. The analysis of the switching energy reduction is presented. Experiments were carried out on a 10-bit SAR-ADC designed using a 0.35 mu m CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design