Optogenetics-Inspired Tunable Synaptic Functions in Memristors

Two-terminal memristors with internal Ca²⁺-like dynamics can be used to faithfully emulate biological synaptic functions and have been intensively studied for neural network implementations. Inspired by the optogenetic technique that utilizes light to tune the Ca²⁺ dynamics and subsequently the synaptic plasticity, we develop a CH₃NH₃PbI₃ (MAPbI₃)-based memristor that exhibits light-tunable synaptic behaviors. Specifically, we show that by increasing the formation energy of iodine vacancy (V_I^·/V_I^×), light illumination can be used to control the V_I^·/V_I^× generation and annihilation dynamics, resembling light-controlled Ca²⁺ influx in biological synapses. We demonstrate that the memory formation and memory loss behaviors in the memristors can be modified by controlling the intensity and the wavelength of the illuminated light. Coincidence detection of electrical and light stimulations is also implemented in the memristive device with real-time (≤20 ms) response to light illumination. These results open options to modify the synaptic plasticity effects in memristor-based neuromorphic systems and can lead to the development of electronic systems that can faithfully emulate diverse biological processes

Tuning Resistive Switching Characteristics of Tantalum Oxide Memristors through Si Doping

An oxide memristor device changes its internal state according to the history of the applied voltage and current. The principle of resistive switching (RS) is based on ion transport (<i>e.g.</i>, oxygen vacancy redistribution). To date, devices with bi-, triple-, or even quadruple-layered structures have been studied to achieve the desired switching behavior through device structure optimization. In contrast, the device performance can also be tuned through fundamental atomic-level design of the switching materials, which can directly affect the dynamic transport of ions and lead to optimized switching characteristics. Here, we show that doping tantalum oxide memristors with silicon atoms can facilitate oxygen vacancy formation and transport in the switching layer with adjustable ion hopping distance and drift velocity. The devices show larger dynamic ranges with easier access to the intermediate states while maintaining the extremely high cycling endurance (>10¹⁰ set and reset) and are well-suited for neuromorphic computing applications. As an example, we demonstrate different flavors of spike-timing-dependent plasticity in this memristor system. We further provide a characterization methodology to quantitatively estimate the effective hopping distance of the oxygen vacancies. The experimental results are confirmed through detailed <i>ab initio</i> calculations which reveal the roles of dopants and provide design methodology for further optimization of the RS behavior

Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor

Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a ⟨111⟩ Si substrate were fabricated and analyzed. Because of efficient gate coupling in the nanowire-GAA transistor structure and the high density one-dimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with <i>I</i>_on of 750 μA/μm were obtained at a moderate gate length of 544 nm with minimal short-channel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confidence of single nanowire operation. Using two vertical nanowire junctionless transistors, a PMOS-logic inverter with near rail-to-rail output voltage was demonstrated, and device matching in the logic can be conveniently obtained by controlling the number of nanowires employed in different devices rather than modifying device geometry. These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform

Tuning Ionic Transport in Memristive Devices by Graphene with Engineered Nanopores

Memristors, based on inherent memory effects in simple two-terminal structures, have attracted tremendous interest recently for applications ranging from nonvolatile data storage to neuromorphic computing based on non-von Neumann architectures. In a memristor, the ability to modulate and retain the state of an internal variable leads to experimentally observed resistive switching (RS) effects. Such phenomena originate from internal, microscopic ionic migration and associated electrochemical processes that modify the materials’ electrical and other physical properties. To optimize the device performance for practical applications with large-size arrays, controlling the internal ionic transport and redox reaction processes thus becomes a necessity, ideally at the atomic scale. Here we show that the RS characteristics in tantalum-oxide-based memristors can be systematically tuned by inserting a graphene film with engineered nanopores. Graphene, with its atomic thickness and excellent impermeability and chemical stability, can be effectively integrated into the device stack and can offer unprecedented capabilities for the control of ionic dynamics at the nanoscale. In this device structure, the graphene film effectively blocks ionic transport and redox reactions; thereby the oxygen vacancies required during the RS process are allowed to transport only through the engineered nanosized openings in the graphene layer, leading to effective modulation of the device performance by controlling the nanopore size in graphene. The roles of graphene as an ion-blocking layer in the device structure were further supported by transmission electron microscopy, energy-dispersive X-ray spectroscopy, and atomistic simulations based on first-principles calculations

<i>K</i>‑means Data Clustering with Memristor Networks

Memristor-based neuromorphic networks have been actively studied as a promising candidate to overcome the von-Neumann bottleneck in future computing applications. Several recent studies have demonstrated memristor network’s capability to perform supervised as well as unsupervised learning, where features inherent in the input are identified and analyzed by comparing with features stored in the memristor network. However, even though in some cases the stored feature vectors can be normalized so that the winning neurons can be directly found by the (input) vector–(stored) vector dot-products, in many other cases, normalization of the feature vectors is not trivial or practically feasible, and calculation of the actual Euclidean distance between the input vector and the stored vector is required. Here we report experimental implementation of memristor crossbar hardware systems that can allow direct comparison of the Euclidean distances without normalizing the weights. The experimental system enables unsupervised <i>K</i>-means clustering algorithm through online learning, and produces high classification accuracy (93.3%) for the standard IRIS data set. The approaches and devices can be used in other unsupervised learning systems, and significantly broaden the range of problems a memristor-based network can solve

Experimental Demonstration of a Second-Order Memristor and Its Ability to Biorealistically Implement Synaptic Plasticity

Memristors have been extensively studied for data storage and low-power computation applications. In this study, we show that memristors offer more than simple resistance change. Specifically, the dynamic evolutions of internal state variables allow an oxide-based memristor to exhibit Ca²⁺-like dynamics that natively encode timing information and regulate synaptic weights. Such a device can be modeled as a second-order memristor and allow the implementation of critical synaptic functions realistically using simple spike forms based solely on spike activity