Deep p-Ring Trench Termination: An Innovative and Cost-Effective Way to Reduce Silicon Area

A new type of high voltage termination, namely the “deep p-ring trench” termination design for high voltage, high power devices is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required, it also removes the need for an additional mask as is the case of the traditional p+ ring type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide which results in reduced hot carrier injection and improved device reliabilit

4.5 kV Bi-mode Gate Commutated Thyristor design with High Power Technology and shallow diode-anode

The Bi-mode Gate Commutated Thyristor (BGCT) is a reverse conducting Gate Commutated Thyristor (GCT) where the diode regions are intertwined with GCT parts. In this work we examine the impact of shallow diode-anodes on the operation of the GCT and propose the introduction of optimised High Power Technology (HPT+) in the GCT part. In order to assess and compare the new designs with the conventional, a multi-cell mixed mode model for large area device modelling was used. The analysis of the simulation results show that the shallow diode does not affect the MCC whereas the introduction of the HPT+ allows for a step improvement

New Bi-Mode Gate-Commutated Thyristor Design Concept for High-Current Controllability and Low ON-State Voltage Drop

© 2016 IEEE. A new design approach for bi-mode gatecommutated thyristors (BGCTs) is proposed for high-current controllability and low ON-state voltage drop. Using a complex multi-cell mixed-mode simulation model which can capture the maximum controllable current (MCC) of large area devices, a failure analysis was performed to demonstrate that the new design concept can increase the MCC by about 27% at room temperature and by about 17% at 400 K while minimizing the ON-state voltage drop. The simulations depict that the improvement comes from the new approach to terminate the GCT part in the BGCT way of intertwining GCT and diode regions for reverse conducting operation

On the Investigation of the "anode Side" SuperJunction IGBT Design Concept

In this letter, we present the "anode-side" SuperJunction trench field stop+ IGBT concept with drift region SuperJunction pillars placed at the anode side of the structure rather than the cathode side. The extent of the pillars toward the cathode side is shown to pose a tradeoff between fabrication technology capabilities (and cost) versus the device performance, by extensive TCAD simulations. The proposed device structure simplifies the fabrication requirements by steering clear from the need to align the cathode side features with the SuperJunction pillars. It also provides an extra degree of freedom by decoupling the cathode design from the SuperJunction structure. Additionally, the presence of SuperJunction technology in the drift region of the "anode-side" SJ Trench FS+ IGBT results in 20% reduction of ON-state losses for the same switching energy losses or, up to 30% switching losses reduction for the same ON-state voltage drop, compared with a 1.2-kV breakdown rated conventional FS+ Trench IGBT device. The proposed structure also finds applications in reverse conducting IGBTs, where a reduced snapback can be achieved, and in MOS-controlled thyristor devices

An experimental demonstration of a 4.5 kV “Bi-mode Gate Commutated Thyristor” (BGCT)

In this work we present the first experimental results of a Bi-mode Gate Commutated Thyristor (BGCT). The BGCT is a new type of Reverse Conducting-Integrated Gate Commutated Thyristor (RC-IGCT). In a conventional RC-IGCT, the IGCT and diode are integrated into a single wafer but they are fully separated from each other. The novel BGCT on the other hand features an interdigitated integration of diode- and GCT-areas. This interdigitated integration results in an improved diode as well as GCT area, better thermal distribution, soft turn-off/reverse recovery and lower leakage current compared to conventional RC-IGCTs. We have discussed the advantages of a new diode anode design in BGCT, which is shallower than that of the conventional RC-IGCT. We have successfully demonstrated the BGCT concept with 38 mm, 4.5 kV prototypes and compared the on-state, turn-off and blocking characteristics with conventional RC-IGCTs both in GCT- and diode-modes of operation

Optimal gate commutated thyristor design for bi-mode gate commutated thyristors underpinning high, temperature independent, current controllability

The Bi-mode Gate Commutated Thyristor (BGCT) is an advanced reverse conducting device aiming high power applications. Due to the high degree of interdigitation of diode parts and Gate Commutated Thyristor (GCT) parts, it is necessary to investigate how to best separate the two and at the same time, how to maximise the individual power handling capability. This work underpins the latter, for the GCT part. In achieving that, this letter details the optimisation direction, identifies the design parameters that influence the Maximum Controllable Current (MCC) and thereafter introduces a new design attribute, the “p-zone”. This new design not only improves the MCC at high temperature, but also at low temperature, yielding temperature independent current handling capability and at least 1000 A, or 23.5 % of improvement compared to the state-of-the-art. As a result, the proposed design constitutes an enabler for optimally designed bi-mode devices rated at least 5000 A for applications with the highest power requirement

Improving Current Controllability in Bi-Mode Gate Commutated Thyristors

The Bi-mode gate commutated thyristor (BGCT) is a new type of reverse conducting Gate Commutated Thyristor (GCT). This paper focuses on the maximum controllable current capability of BGCTs and proposes new solutions which can increase it. The impact of proposed solutions in the turn-ON and turn-OFF is also assessed. For this analysis, a 2-D mixed mode model for full-wafer device simulations has been developed and utilized