RIOT: a simple graphical assembly tool

Errors in the chip assembly process are harder to find than errors in cell design, since they belong to no specific part of the design, but rather to the assembly as a whole. Assembly errors are more costly than call design errors also, since they often go unnoticed until late in the design cycle. Interactive graphic tools typically require that assembly be done with primitive graphical operations, which are inappropriate far the assembly task. Language-based tools give more powerful assembly operations, but remove the two dimensional view of the chip necessary to visualize many assembly operations. Riot is a simple Interactive graphical tool designed to facilitate the assembly of cells into integrated systems. Riot supplies the user with primitive operations of connection -- abutment, routing and stretching - in an interactive graphic environment. Thus, the designer retains full control of the design, including the assignment of positions to instances of cells and the choice of connection mechanism. The computer takes care of the tedious and exacting implementation detail, guaranteeing that connections are actually made. The powerful connection primitives give the user of Riot the ability to quickly assemble a custom chip from a collection of low-level cells. This document provides a discussion of the motivation for Riot and a description of the Riot chip assembly system, its capabilities and its use

A Comprehensive CIF Test Set

No abstract

A Comparison of MOS PLAs

This paper discusses Pl.A designs in three MOS technologies: NMOS, CMOS/SOS and CMOS-Bulk. The purpose of this paper is not to introduce a new and exciting PLA design, nor is it to recommend one fabrication technology over another. Its purpose is to use PLAs as a standard, hopefully familiar layout strategy so that new designers can get a better understanding of the advantages and disadvantages of all three technologies from a designer's viewpoint. It is hoped that this paper will provide more data to those who must select a technology for their integrated circuit fabrication

CIFSYM -- CIF Symbol Handler

No Abstract

GIGI Terminals at Caltech

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Combining graphics and layout language in a single interactive system

Layout languages provide users with the capability to algorithmically define cells. But the specification language is so non-intuitive that it is impossible to debug a design in that language, one must plot it. Interactive graphics systems, on the other hand, allow the user to debug in the form in which he sees the design, but severely restrict the language he may use to express the graphics. For example, he cannot express loops or conditionals. What is really needed is a single interactive system that combines layout language and graphic modifications to the data. This paper describes just such a system

The Caltech Intermediate Form for LSI Layout Description

No Abstract

Chip assembly tools

In large-scale integrated circuit design, chip assembly is more difficult, more time consuming. and more error prone than the design of the low-level cells. Assembly errors tend to persist until late in the design cycle requiring extensive rework. Unfortunately, the tools traditionally provided for custom integrated circuit design address the problems of cell design well, but do not properly address the problems of chip assembly. A great deal of emphasis at Caltech has been placed on tools that do address chip assembly. This paper reports on some of these tools