Upregulation of the Wnt Co-Receptor LRP6 Promotes Hepatocarcinogenesis and Enhances Cell Invasion

Background: Activation of the Wnt/b-catenin signaling pathway plays a crucial role in hepatocellular carcinoma (HCC). Lowdensity lipoprotein (LDL) receptor-related protein-6 (LRP6) is one of the co-receptors of the Wnt/b-catenin pathway and forms a signaling complex with Wnt ligand and Frizzled receptor to activate downstream signaling. However, the role of LRP6 in hepatocarcinogenesis is unclear. In this study, we examined its expression and roles in human HCC. Methodology/Principal Findings: Using real-time quantitative RT-PCR, we found that LRP6 was frequently (45%) overexpressed in human HCCs (P = 0.003). In vitro studies showed that ectopic expression of LRP6 increased the protein level of b-catenin. Moreover, overexpression of the full-length and constitutively active LRP6, respectively, activated the WNT/b-catenin signaling pathway, as shown by the TCF/b-catenin reporter assay. With regard to the effects of LRP6 overexpression in HCC cells, stable overexpression of the constitutively active LRP6 in BEL-7402 HCC cells enhanced cell proliferation, cell migration, and invasion in vitro as well as tumorigenicity in nude mice. Conclusions/Significance: Our findings indicate that overexpression of LRP6 contributes to the hyperactivation of the Wnt

Deleted in Liver Cancer 2 (DLC2) Was Dispensable for Development and Its Deficiency Did Not Aggravate Hepatocarcinogenesis

DLC2 (deleted in liver cancer 2), a Rho GTPase-activating protein, was previously shown to be underexpressed in human hepatocellular carcinoma and has tumor suppressor functions in cell culture models. We generated DLC2-deficient mice to investigate the tumor suppressor role of DLC2 in hepatocarcinogenesis and the function of DLC2 in vivo. In this study, we found that, unlike homologous DLC1, which is essential for embryonic development, DLC2 was dispensable for embryonic development and DLC2-deficient mice could survive to adulthood. We also did not observe a higher incidence of liver tumor formation or diethylnitrosamine (DEN)-induced hepatocarcinogenesis in DLC2-deficient mice. However, we observed that DLC2-deficient mice were smaller and had less adipose tissue than the wild type mice. These phenotypes were not due to reduction of cell size or defect in adipogenesis, as observed in the 190B RhoGAP-deficient mouse model. Together, these results suggest that deficiency in DLC2 alone does not enhance hepatocarcinogenesis

On the Design of a Self-Reconfigurable SoPC Based Cryptographic Engine

Abstract — This paper presents a SoPC (System-ona-Programmable-Chip) embedded system featuring selfreconfigurable capability. It addresses the factors that limit the system performance when FPGAs are used to implement various encryption algorithms dynamically. The limiting factors are the data transfer rate between the host and the FPGA, and the reconfiguration latency. The results generated by the cryptographic engine reported in this paper show that in order to attain optimal performance, it is crucial to floor-plan the reconfigurable part of the FPGA

Practical Design of a Computation and Energy Efficient Hardware Task Scheduler in Embedded Reconfigurable Computing Systems

By utilizing massively parallel circuit design in FP-GAs, the overall system efficiency, in terms of computation efficiency and energy efficiency, can be greatly enhanced by offloading some computation-intensive tasks which are originally executed in the instruction set processor to the FPGA fabric. In essence, a hardware task scheduler is needed. However, most of the work in the literature considers scheduling algorithms which are unable or difficult to be implemented using the design flows in current development platform. Moreover, little of the work takes energy consumption into consideration. In this paper, we present the design of a hardware task scheduler which takes energy consumption into consideration, and can be readily implemented using current design flows. 1

High performance embedded reconfigurable computing: data security and media processing applications

abstractpublished_or_final_versionElectrical and Electronic EngineeringMasterMaster of Philosoph

Multi-core design and resource allocation: from big core to ultra-tiny core

published_or_final_versionElectrical and Electronic EngineeringDoctoralDoctor of Philosoph

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads. Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCFC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8 mu m CMOS process with V-m = 0.72 V and V-tp = -0.75 V, For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51 degrees phase margin, 0.33-V/mu s slew rate, 3.54-mu s settling time, and 426-mu W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase on the power consumption

Simple method to design resonant circuits of electronic ballast for fluorescent lamps

A simple design method has been developed to investigate the dimming control of electronic ballast circuits for fluorescent lamps. This method is based on the steady-state calculation of the ballast at resonant frequency, f0, and the inherent characteristics of the fluorescent lamp, i.e. the relationship between the lamp resistance and the lamp power. The inherent lamp characteristics encompass the fact that the voltage across the lamp varies with the lamp power. Including this inherent characteristic into a new lamp Spice simulation model can provide an accurate simulation result of the relations between the ballast operation frequency and the lamp power

Phase-controlled dimmable CFL with PPFC and switching frequency modulation

A dimmable compact fluorescent lamp using a commercial triac dimmer is presented. To achieve a power factor of 0.93 at full intensity, a valley-filled charge pump passive power factor corrector is used. To achieve stable control at low intensity, a novel application of switching frequency modulation is introduced